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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Diff between revs 504 and 562

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Rev 504 Rev 562
Line 43... Line 43...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.1  2002/01/03 08:16:15  lampret
 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
 
//
// Revision 1.19  2001/11/30 18:59:47  simons
// Revision 1.19  2001/11/30 18:59:47  simons
// *** empty log message ***
// *** empty log message ***
//
//
// Revision 1.18  2001/11/23 21:42:31  simons
// Revision 1.18  2001/11/23 21:42:31  simons
// Program counter divided to PPC and NPC.
// Program counter divided to PPC and NPC.
Line 236... Line 239...
wire    [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
wire    [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
wire    [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
wire    [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
wire    [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
wire    [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
wire    [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
wire    [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
 
wire                            genpc_freeze;
wire                            if_freeze;
wire                            if_freeze;
wire                            id_freeze;
wire                            id_freeze;
wire                            ex_freeze;
wire                            ex_freeze;
wire                            wb_freeze;
wire                            wb_freeze;
wire    [`OR1200_SEL_WIDTH-1:0]  sel_a;
wire    [`OR1200_SEL_WIDTH-1:0]  sel_a;
Line 366... Line 370...
        .taken(branch_taken),
        .taken(branch_taken),
        .binsn_addr(lr_sav),
        .binsn_addr(lr_sav),
        .epcr(epcr),
        .epcr(epcr),
        .spr_dat_i(spr_dataout),
        .spr_dat_i(spr_dataout),
        .spr_pc_we(pc_we),
        .spr_pc_we(pc_we),
        .genpc_refetch(genpc_refetch)
        .genpc_refetch(genpc_refetch),
 
        .genpc_freeze(genpc_freeze),
 
        .flushpipe(flushpipe)
);
);
 
 
//
//
// Instantiation of instruction fetch block
// Instantiation of instruction fetch block
//
//
Line 638... Line 644...
        .if_stall(if_stall),
        .if_stall(if_stall),
        .lsu_unstall(lsu_unstall),
        .lsu_unstall(lsu_unstall),
        .force_dslot_fetch(force_dslot_fetch),
        .force_dslot_fetch(force_dslot_fetch),
        .du_stall(du_stall),
        .du_stall(du_stall),
        .mac_stall(mac_stall),
        .mac_stall(mac_stall),
 
        .genpc_freeze(genpc_freeze),
        .if_freeze(if_freeze),
        .if_freeze(if_freeze),
        .id_freeze(id_freeze),
        .id_freeze(id_freeze),
        .ex_freeze(ex_freeze),
        .ex_freeze(ex_freeze),
        .wb_freeze(wb_freeze)
        .wb_freeze(wb_freeze)
);
);
Line 678... Line 685...
        .except_start(except_start),
        .except_start(except_start),
        .except_started(except_started),
        .except_started(except_started),
        .except_stop(except_stop),
        .except_stop(except_stop),
        .wb_pc(spr_dat_ppc),
        .wb_pc(spr_dat_ppc),
        .ex_pc(spr_dat_npc),
        .ex_pc(spr_dat_npc),
 
        .id_pc(),
 
//      .wb_pc(),
 
//      .ex_pc(spr_dat_ppc),
 
//      .id_pc(spr_dat_npc),
 
 
        .datain(operand_b),
        .datain(operand_b),
        .du_dsr(du_dsr),
        .du_dsr(du_dsr),
        .epcr_we(epcr_we),
        .epcr_we(epcr_we),
        .eear_we(eear_we),
        .eear_we(eear_we),

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