| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/01/18 14:21:43 lampret
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// Fixed 'the NPC single-step fix'.
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//
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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| Line 294... |
Line 297... |
wire [31:0] spr_dat_rf;
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wire [31:0] spr_dat_rf;
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wire [31:0] spr_dat_npc;
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wire [31:0] spr_dat_npc;
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wire [31:0] spr_dat_ppc;
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wire [31:0] spr_dat_ppc;
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wire [31:0] spr_dat_mac;
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wire [31:0] spr_dat_mac;
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wire force_dslot_fetch;
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wire force_dslot_fetch;
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wire has_dslot;
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wire no_more_dslot;
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wire ex_void;
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wire ex_void;
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wire if_stall;
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wire if_stall;
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wire id_macrc_op;
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wire id_macrc_op;
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wire ex_macrc_op;
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wire ex_macrc_op;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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| Line 314... |
Line 317... |
wire except_illegal;
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wire except_illegal;
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wire except_itlbmiss;
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wire except_itlbmiss;
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wire except_immufault;
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wire except_immufault;
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wire except_ibuserr;
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wire except_ibuserr;
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wire except_dbuserr;
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wire except_dbuserr;
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wire abort_ex;
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//
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//
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// icpu_we_o
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// icpu_we_o
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//
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//
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assign icpu_we_o = 1'b0;
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assign icpu_we_o = 1'b0;
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| Line 380... |
Line 384... |
.epcr(epcr),
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.epcr(epcr),
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.spr_dat_i(spr_dataout),
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.spr_dat_i(spr_dataout),
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.spr_pc_we(pc_we),
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.spr_pc_we(pc_we),
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.genpc_refetch(genpc_refetch),
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.genpc_refetch(genpc_refetch),
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.genpc_freeze(genpc_freeze),
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.genpc_freeze(genpc_freeze),
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.flushpipe(flushpipe)
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.flushpipe(flushpipe),
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.no_more_dslot(no_more_dslot)
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);
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);
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//
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//
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// Instantiation of instruction fetch block
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// Instantiation of instruction fetch block
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//
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//
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| Line 401... |
Line 406... |
.if_freeze(if_freeze),
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.if_freeze(if_freeze),
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.if_insn(if_insn),
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.if_insn(if_insn),
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.if_pc(if_pc),
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.if_pc(if_pc),
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.flushpipe(flushpipe),
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.flushpipe(flushpipe),
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.if_stall(if_stall),
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.if_stall(if_stall),
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.has_dslot(has_dslot),
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.no_more_dslot(no_more_dslot),
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.taken(branch_taken),
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.taken(branch_taken),
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.genpc_refetch(genpc_refetch),
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.genpc_refetch(genpc_refetch),
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.rfe(rfe),
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.rfe(rfe),
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.except_itlbmiss(except_itlbmiss),
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.except_itlbmiss(except_itlbmiss),
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.except_immufault(except_immufault),
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.except_immufault(except_immufault),
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| Line 423... |
Line 428... |
.wb_freeze(wb_freeze),
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.wb_freeze(wb_freeze),
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.flushpipe(flushpipe),
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.flushpipe(flushpipe),
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.if_insn(if_insn),
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.if_insn(if_insn),
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.ex_insn(ex_insn),
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.ex_insn(ex_insn),
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.branch_op(branch_op),
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.branch_op(branch_op),
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.branch_taken(branch_taken),
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.rf_addra(rf_addra),
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.rf_addra(rf_addra),
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.rf_addrb(rf_addrb),
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.rf_addrb(rf_addrb),
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.rf_rda(rf_rda),
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.rf_rda(rf_rda),
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.rf_rdb(rf_rdb),
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.rf_rdb(rf_rdb),
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.alu_op(alu_op),
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.alu_op(alu_op),
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| Line 446... |
Line 452... |
.spr_addrimm(spr_addrimm),
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.spr_addrimm(spr_addrimm),
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.wbforw_valid(wbforw_valid),
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.wbforw_valid(wbforw_valid),
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.sig_syscall(sig_syscall),
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.sig_syscall(sig_syscall),
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.sig_trap(sig_trap),
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.sig_trap(sig_trap),
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.force_dslot_fetch(force_dslot_fetch),
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.force_dslot_fetch(force_dslot_fetch),
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.has_dslot(has_dslot),
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.no_more_dslot(no_more_dslot),
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.ex_void(ex_void),
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.ex_void(ex_void),
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.id_macrc_op(id_macrc_op),
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.id_macrc_op(id_macrc_op),
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.ex_macrc_op(ex_macrc_op),
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.ex_macrc_op(ex_macrc_op),
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.rfe(rfe),
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.rfe(rfe),
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.except_illegal(except_illegal)
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.except_illegal(except_illegal)
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| Line 652... |
Line 658... |
.extend_flush(extend_flush),
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.extend_flush(extend_flush),
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.lsu_stall(lsu_stall),
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.lsu_stall(lsu_stall),
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.if_stall(if_stall),
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.if_stall(if_stall),
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.lsu_unstall(lsu_unstall),
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.lsu_unstall(lsu_unstall),
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.force_dslot_fetch(force_dslot_fetch),
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.force_dslot_fetch(force_dslot_fetch),
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.abort_ex(abort_ex),
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.du_stall(du_stall),
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.du_stall(du_stall),
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.mac_stall(mac_stall),
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.mac_stall(mac_stall),
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.genpc_freeze(genpc_freeze),
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.genpc_freeze(genpc_freeze),
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.if_freeze(if_freeze),
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.if_freeze(if_freeze),
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.id_freeze(id_freeze),
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.id_freeze(id_freeze),
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| Line 708... |
Line 715... |
.epcr(epcr),
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.epcr(epcr),
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.eear(eear),
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.eear(eear),
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.esr(esr),
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.esr(esr),
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.lsu_addr(dcpu_adr_o),
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.lsu_addr(dcpu_adr_o),
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.sr(sr)
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.sr(sr),
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.abort_ex(abort_ex)
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);
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);
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//
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//
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// Instantiation of configuration registers
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// Instantiation of configuration registers
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//
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//
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