| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.4 2002/01/28 01:15:59 lampret
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// Revision 1.4 2002/01/28 01:15:59 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.3 2002/01/18 14:21:43 lampret
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// Revision 1.3 2002/01/18 14:21:43 lampret
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// Fixed 'the NPC single-step fix'.
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// Fixed 'the NPC single-step fix'.
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| Line 262... |
Line 265... |
if (rst)
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if (rst)
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spr_addrimm <= #1 16'h0000;
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spr_addrimm <= #1 16'h0000;
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else if (!ex_freeze & id_freeze | flushpipe)
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else if (!ex_freeze & id_freeze | flushpipe)
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spr_addrimm <= #1 16'h0000;
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spr_addrimm <= #1 16'h0000;
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else if (!ex_freeze) begin
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else if (!ex_freeze) begin
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case (id_insn[31:26]) // synopsys full_case parallel_case
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case (id_insn[31:26]) // synopsys parallel_case
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// l.mfspr
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// l.mfspr
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`OR1200_OR32_MFSPR:
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`OR1200_OR32_MFSPR:
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spr_addrimm <= #1 id_insn[15:0];
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spr_addrimm <= #1 id_insn[15:0];
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// l.mtspr
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// l.mtspr
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default:
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default:
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| Line 277... |
Line 280... |
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//
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//
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// Decode of multicycle
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// Decode of multicycle
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//
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//
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always @(id_insn) begin
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always @(id_insn) begin
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case (id_insn[31:26]) // synopsys full_case parallel_case
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case (id_insn[31:26]) // synopsys parallel_case
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`ifdef UNUSED
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`ifdef UNUSED
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// l.lwz
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// l.lwz
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`OR1200_OR32_LWZ:
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`OR1200_OR32_LWZ:
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multicycle = `OR1200_TWO_CYCLES;
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multicycle = `OR1200_TWO_CYCLES;
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| Line 328... |
Line 331... |
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//
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//
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// Decode of imm_signextend
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// Decode of imm_signextend
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//
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//
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always @(id_insn) begin
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always @(id_insn) begin
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case (id_insn[31:26]) // synopsys full_case parallel_case
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case (id_insn[31:26]) // synopsys parallel_case
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// l.addi
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// l.addi
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`OR1200_OR32_ADDI:
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`OR1200_OR32_ADDI:
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imm_signextend = 1'b1;
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imm_signextend = 1'b1;
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| Line 368... |
Line 371... |
//
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//
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// LSU addr offset
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// LSU addr offset
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//
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//
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always @(lsu_op or ex_insn) begin
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always @(lsu_op or ex_insn) begin
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lsu_addrofs[10:0] = ex_insn[10:0];
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lsu_addrofs[10:0] = ex_insn[10:0];
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case(lsu_op) // synopsys parallel_case full_case
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case(lsu_op) // synopsys parallel_case
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`OR1200_LSUOP_SW, `OR1200_LSUOP_SH, `OR1200_LSUOP_SB :
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`OR1200_LSUOP_SW, `OR1200_LSUOP_SH, `OR1200_LSUOP_SB :
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lsu_addrofs[31:11] = {{16{ex_insn[25]}}, ex_insn[25:21]};
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lsu_addrofs[31:11] = {{16{ex_insn[25]}}, ex_insn[25:21]};
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default :
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default :
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lsu_addrofs[31:11] = {{16{ex_insn[15]}}, ex_insn[15:11]};
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lsu_addrofs[31:11] = {{16{ex_insn[15]}}, ex_insn[15:11]};
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endcase
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endcase
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| Line 385... |
Line 388... |
if (rst)
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if (rst)
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rf_addrw <= #1 5'd0;
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rf_addrw <= #1 5'd0;
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else if (!ex_freeze & id_freeze)
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else if (!ex_freeze & id_freeze)
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rf_addrw <= #1 5'd00;
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rf_addrw <= #1 5'd00;
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else if (!ex_freeze)
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else if (!ex_freeze)
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case (pre_branch_op) // synopsys parallel_case full_case
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case (pre_branch_op) // synopsys parallel_case
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`OR1200_BRANCHOP_JR, `OR1200_BRANCHOP_BAL:
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`OR1200_BRANCHOP_JR, `OR1200_BRANCHOP_BAL:
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rf_addrw <= #1 5'd09; // link register r9
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rf_addrw <= #1 5'd09; // link register r9
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default:
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default:
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rf_addrw <= #1 id_insn[25:21];
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rf_addrw <= #1 id_insn[25:21];
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endcase
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endcase
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| Line 459... |
Line 462... |
//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst)
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if (rst)
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sel_imm <= #1 1'b0;
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sel_imm <= #1 1'b0;
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else if (!id_freeze) begin
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else if (!id_freeze) begin
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case (if_insn[31:26]) // synopsys full_case parallel_case
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case (if_insn[31:26]) // synopsys parallel_case
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// j.jalr
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// j.jalr
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`OR1200_OR32_JALR:
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`OR1200_OR32_JALR:
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sel_imm <= #1 1'b0;
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sel_imm <= #1 1'b0;
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| Line 532... |
Line 535... |
if (rst)
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if (rst)
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except_illegal <= #1 1'b0;
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except_illegal <= #1 1'b0;
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else if (!ex_freeze & id_freeze | flushpipe)
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else if (!ex_freeze & id_freeze | flushpipe)
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except_illegal <= #1 1'b0;
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except_illegal <= #1 1'b0;
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else if (!ex_freeze) begin
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else if (!ex_freeze) begin
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case (id_insn[31:26]) // synopsys full_case parallel_case
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case (id_insn[31:26]) // synopsys parallel_case
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`OR1200_OR32_J,
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`OR1200_OR32_J,
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`OR1200_OR32_JAL,
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`OR1200_OR32_JAL,
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`OR1200_OR32_JALR,
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`OR1200_OR32_JALR,
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`OR1200_OR32_JR,
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`OR1200_OR32_JR,
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| Line 586... |
Line 589... |
if (rst)
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if (rst)
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alu_op <= #1 `OR1200_ALUOP_NOP;
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alu_op <= #1 `OR1200_ALUOP_NOP;
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else if (!ex_freeze & id_freeze | flushpipe)
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else if (!ex_freeze & id_freeze | flushpipe)
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alu_op <= #1 `OR1200_ALUOP_NOP;
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alu_op <= #1 `OR1200_ALUOP_NOP;
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else if (!ex_freeze) begin
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else if (!ex_freeze) begin
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case (id_insn[31:26]) // synopsys full_case parallel_case
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case (id_insn[31:26]) // synopsys parallel_case
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// l.j
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// l.j
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`OR1200_OR32_J:
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`OR1200_OR32_J:
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alu_op <= #1 `OR1200_ALUOP_IMM;
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alu_op <= #1 `OR1200_ALUOP_IMM;
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| Line 675... |
Line 678... |
if (rst)
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if (rst)
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mac_op <= #1 `OR1200_MACOP_NOP;
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mac_op <= #1 `OR1200_MACOP_NOP;
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else if (!ex_freeze & id_freeze | flushpipe)
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else if (!ex_freeze & id_freeze | flushpipe)
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mac_op <= #1 `OR1200_MACOP_NOP;
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mac_op <= #1 `OR1200_MACOP_NOP;
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else if (!ex_freeze)
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else if (!ex_freeze)
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case (id_insn[31:26]) // synopsys full_case parallel_case
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case (id_insn[31:26]) // synopsys parallel_case
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// l.maci
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// l.maci
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`OR1200_OR32_MACI:
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`OR1200_OR32_MACI:
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mac_op <= #1 `OR1200_MACOP_MAC;
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mac_op <= #1 `OR1200_MACOP_MAC;
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| Line 717... |
Line 720... |
if (rst)
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if (rst)
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rfwb_op <= #1 `OR1200_RFWBOP_NOP;
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rfwb_op <= #1 `OR1200_RFWBOP_NOP;
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else if (!ex_freeze & id_freeze | flushpipe)
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else if (!ex_freeze & id_freeze | flushpipe)
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rfwb_op <= #1 `OR1200_RFWBOP_NOP;
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rfwb_op <= #1 `OR1200_RFWBOP_NOP;
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else if (!ex_freeze) begin
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else if (!ex_freeze) begin
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case (id_insn[31:26]) // synopsys full_case parallel_case
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case (id_insn[31:26]) // synopsys parallel_case
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// j.jal
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// j.jal
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`OR1200_OR32_JAL:
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`OR1200_OR32_JAL:
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rfwb_op <= #1 `OR1200_RFWBOP_LR;
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rfwb_op <= #1 `OR1200_RFWBOP_LR;
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| Line 805... |
Line 808... |
if (rst)
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if (rst)
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pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
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pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
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else if (flushpipe)
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else if (flushpipe)
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pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
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pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
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else if (!id_freeze) begin
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else if (!id_freeze) begin
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case (if_insn[31:26]) // synopsys full_case parallel_case
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case (if_insn[31:26]) // synopsys parallel_case
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// l.j
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// l.j
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`OR1200_OR32_J:
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`OR1200_OR32_J:
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pre_branch_op <= #1 `OR1200_BRANCHOP_BAL;
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pre_branch_op <= #1 `OR1200_BRANCHOP_BAL;
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| Line 863... |
Line 866... |
if (rst)
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if (rst)
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lsu_op <= #1 `OR1200_LSUOP_NOP;
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lsu_op <= #1 `OR1200_LSUOP_NOP;
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else if (!ex_freeze & id_freeze | flushpipe)
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else if (!ex_freeze & id_freeze | flushpipe)
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lsu_op <= #1 `OR1200_LSUOP_NOP;
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lsu_op <= #1 `OR1200_LSUOP_NOP;
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else if (!ex_freeze) begin
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else if (!ex_freeze) begin
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case (id_insn[31:26]) // synopsys full_case parallel_case
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case (id_insn[31:26]) // synopsys parallel_case
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// l.lwz
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// l.lwz
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`OR1200_OR32_LWZ:
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`OR1200_OR32_LWZ:
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lsu_op <= #1 `OR1200_LSUOP_LWZ;
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lsu_op <= #1 `OR1200_LSUOP_LWZ;
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