| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.7 2002/03/29 15:16:55 lampret
|
|
// Some of the warnings fixed.
|
|
//
|
// Revision 1.6 2002/03/28 19:10:40 lampret
|
// Revision 1.6 2002/03/28 19:10:40 lampret
|
// Optimized cache controller FSM.
|
// Optimized cache controller FSM.
|
//
|
//
|
// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
|
// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
|
// First import of the "new" XESS XSV environment.
|
// First import of the "new" XESS XSV environment.
|
| Line 104... |
Line 107... |
module or1200_dc_fsm(
|
module or1200_dc_fsm(
|
// Clock and reset
|
// Clock and reset
|
clk, rst,
|
clk, rst,
|
|
|
// Internal i/f to top level DC
|
// Internal i/f to top level DC
|
dc_en, dcdmmu_cycstb_i, dcdmmu_ci_i, dcpu_we_i, dcpu_sel_i,
|
dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
|
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
|
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
|
dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
|
dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
|
burst, tag_we, dc_addr
|
burst, tag_we, dc_addr
|
);
|
);
|
|
|
| Line 116... |
Line 119... |
// I/O
|
// I/O
|
//
|
//
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
input dc_en;
|
input dc_en;
|
input dcdmmu_cycstb_i;
|
input dcqmem_cycstb_i;
|
input dcdmmu_ci_i;
|
input dcqmem_ci_i;
|
input dcpu_we_i;
|
input dcqmem_we_i;
|
input [3:0] dcpu_sel_i;
|
input [3:0] dcqmem_sel_i;
|
input tagcomp_miss;
|
input tagcomp_miss;
|
input biudata_valid;
|
input biudata_valid;
|
input biudata_error;
|
input biudata_error;
|
input [31:0] start_addr;
|
input [31:0] start_addr;
|
output [31:0] saved_addr;
|
output [31:0] saved_addr;
|
| Line 150... |
Line 153... |
wire first_store_hit_ack;
|
wire first_store_hit_ack;
|
|
|
//
|
//
|
// Generate of DCRAM write enables
|
// Generate of DCRAM write enables
|
//
|
//
|
assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcpu_sel_i;
|
assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcqmem_sel_i;
|
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
|
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
|
|
|
//
|
//
|
// BIU read and write
|
// BIU read and write
|
//
|
//
|
| Line 168... |
Line 171... |
// Assert for cache hit first word ready
|
// Assert for cache hit first word ready
|
// Assert for store cache hit first word ready
|
// Assert for store cache hit first word ready
|
// Assert for cache miss first word stored/loaded OK
|
// Assert for cache miss first word stored/loaded OK
|
// Assert for cache miss first word stored/loaded with an error
|
// Assert for cache miss first word stored/loaded with an error
|
//
|
//
|
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcdmmu_ci_i | first_store_hit_ack;
|
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcqmem_ci_i | first_store_hit_ack;
|
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcdmmu_ci_i;
|
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcqmem_ci_i;
|
assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
|
assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
|
assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
|
assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
|
|
|
//
|
//
|
// Assert burst when doing reload of complete cache line
|
// Assert burst when doing reload of complete cache line
|
| Line 199... |
Line 202... |
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else
|
else
|
case (state) // synopsys parallel_case
|
case (state) // synopsys parallel_case
|
`OR1200_DCFSM_IDLE :
|
`OR1200_DCFSM_IDLE :
|
if (dc_en & dcdmmu_cycstb_i & dcpu_we_i) begin // store
|
if (dc_en & dcqmem_cycstb_i & dcqmem_we_i) begin // store
|
state <= #1 `OR1200_DCFSM_CSTORE;
|
state <= #1 `OR1200_DCFSM_CSTORE;
|
saved_addr_r <= #1 start_addr;
|
saved_addr_r <= #1 start_addr;
|
hitmiss_eval <= #1 1'b1;
|
hitmiss_eval <= #1 1'b1;
|
store <= #1 1'b1;
|
store <= #1 1'b1;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else if (dc_en & dcdmmu_cycstb_i) begin // load
|
else if (dc_en & dcqmem_cycstb_i) begin // load
|
state <= #1 `OR1200_DCFSM_CLOAD;
|
state <= #1 `OR1200_DCFSM_CLOAD;
|
saved_addr_r <= #1 start_addr;
|
saved_addr_r <= #1 start_addr;
|
hitmiss_eval <= #1 1'b1;
|
hitmiss_eval <= #1 1'b1;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
load <= #1 1'b1;
|
load <= #1 1'b1;
|
| Line 222... |
Line 225... |
store <= #1 1'b0;
|
store <= #1 1'b0;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
`OR1200_DCFSM_CLOAD: begin // load
|
`OR1200_DCFSM_CLOAD: begin // load
|
if (dcdmmu_cycstb_i & dcdmmu_ci_i)
|
if (dcqmem_cycstb_i & dcqmem_ci_i)
|
cache_inhibit <= #1 1'b1;
|
cache_inhibit <= #1 1'b1;
|
if (hitmiss_eval)
|
if (hitmiss_eval)
|
saved_addr_r[31:13] <= #1 start_addr[31:13];
|
saved_addr_r[31:13] <= #1 start_addr[31:13];
|
if ((hitmiss_eval & !dcdmmu_cycstb_i) || // load aborted (usually caused by DMMU)
|
if ((hitmiss_eval & !dcqmem_cycstb_i) || // load aborted (usually caused by DMMU)
|
(biudata_error) || // load terminated with an error
|
(biudata_error) || // load terminated with an error
|
((cache_inhibit | dcdmmu_ci_i) & biudata_valid)) begin // load from cache-inhibited area
|
((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // load from cache-inhibited area
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
|
else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
|
state <= #1 `OR1200_DCFSM_LREFILL3;
|
state <= #1 `OR1200_DCFSM_LREFILL3;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
cnt <= #1 `OR1200_DCLS-2;
|
cnt <= #1 `OR1200_DCLS-2;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else if (!tagcomp_miss & !dcdmmu_ci_i) begin // load hit, finish immediately
|
else if (!tagcomp_miss & !dcqmem_ci_i) begin // load hit, finish immediately
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else // load in-progress
|
else // load in-progress
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
end
|
end
|
`OR1200_DCFSM_LREFILL3 : begin
|
`OR1200_DCFSM_LREFILL3 : begin
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
cnt <= #1 cnt - 'd1;
|
cnt <= #1 cnt - 1'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
end
|
end
|
else if (biudata_valid) begin // last load of line refill
|
else if (biudata_valid) begin // last load of line refill
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
end
|
end
|
end
|
end
|
`OR1200_DCFSM_CSTORE: begin // store
|
`OR1200_DCFSM_CSTORE: begin // store
|
if (dcdmmu_cycstb_i & dcdmmu_ci_i)
|
if (dcqmem_cycstb_i & dcqmem_ci_i)
|
cache_inhibit <= #1 1'b1;
|
cache_inhibit <= #1 1'b1;
|
if (hitmiss_eval)
|
if (hitmiss_eval)
|
saved_addr_r[31:13] <= #1 start_addr[31:13];
|
saved_addr_r[31:13] <= #1 start_addr[31:13];
|
if ((hitmiss_eval & !dcdmmu_cycstb_i) || // store aborted (usually caused by DMMU)
|
if ((hitmiss_eval & !dcqmem_cycstb_i) || // store aborted (usually caused by DMMU)
|
(biudata_error) || // store terminated with an error
|
(biudata_error) || // store terminated with an error
|
((cache_inhibit | dcdmmu_ci_i) & biudata_valid)) begin // store to cache-inhibited area
|
((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // store to cache-inhibited area
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
| Line 295... |
Line 298... |
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
end
|
end
|
`ifdef OR1200_DC_STORE_REFILL
|
`ifdef OR1200_DC_STORE_REFILL
|
`OR1200_DCFSM_SREFILL4 : begin
|
`OR1200_DCFSM_SREFILL4 : begin
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
cnt <= #1 cnt - 'd1;
|
cnt <= #1 cnt - 1'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
end
|
end
|
else if (biudata_valid) begin // last load of line refill
|
else if (biudata_valid) begin // last load of line refill
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
end
|
end
|
