| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/01/28 01:15:59 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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| Line 74... |
Line 77... |
`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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`define OR1200_DCFSM_IDLE 3'd0
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`define OR1200_DCFSM_IDLE 3'd0
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`define OR1200_DCFSM_DOLOAD 3'd1
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`define OR1200_DCFSM_CLOAD 3'd1
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`define OR1200_DCFSM_LREFILL3 3'd2
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`define OR1200_DCFSM_LREFILL3 3'd2
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`define OR1200_DCFSM_DOSTORE 3'd3
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`define OR1200_DCFSM_CSTORE 3'd3
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`define OR1200_DCFSM_SREFILL4 3'd4
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`define OR1200_DCFSM_SREFILL4 3'd4
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`define OR1200_DCFSM_ILOAD 3'd5
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`define OR1200_DCFSM_ISTORE 3'd6
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//
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//
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// Data cache FSM for cache line of 16 bytes (4x singleword)
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// Data cache FSM for cache line of 16 bytes (4x singleword)
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//
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//
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| Line 127... |
Line 132... |
reg [2:0] state;
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reg [2:0] state;
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reg [2:0] cnt;
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reg [2:0] cnt;
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reg hitmiss_eval;
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reg hitmiss_eval;
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reg store;
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reg store;
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reg load;
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reg load;
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wire first_store_hit_ack;
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//
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//
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// Generate of DCRAM write enables
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// Generate of DCRAM write enables
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//
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//
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assign dcram_we = {4{load & biudata_valid}} | {4{store & biudata_valid}} & dcpu_sel_i;
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assign dcram_we = {4{load & biudata_valid & (state != `OR1200_DCFSM_ILOAD)}} | {4{first_store_hit_ack}} & dcpu_sel_i;
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//
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//
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// BIU read and write
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// BIU read and write
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//
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//
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assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
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assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
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assign biu_write = store;
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assign biu_write = store;
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//
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//
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// Assert for cache hit first word ready
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// Assert for cache hit first word ready
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// Assert for store cache hit first word ready
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded with an error
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// Assert for cache miss first word stored/loaded with an error
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//
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//
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assign first_hit_ack = (state == `OR1200_DCFSM_DOLOAD) & !tagcomp_miss & !dcdmmu_ci_i | (state == `OR1200_DCFSM_DOSTORE) & !tagcomp_miss & biudata_valid;
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assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss | first_store_hit_ack;
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assign first_miss_ack = ((state == `OR1200_DCFSM_DOLOAD) | (state == `OR1200_DCFSM_DOSTORE)) & (tagcomp_miss | dcdmmu_ci_i) & biudata_valid;
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assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid;
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assign first_miss_err = ((state == `OR1200_DCFSM_DOLOAD) | (state == `OR1200_DCFSM_DOSTORE)) & (tagcomp_miss | dcdmmu_ci_i) & biudata_error;
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assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE) | (state == `OR1200_DCFSM_ILOAD) | (state == `OR1200_DCFSM_ISTORE)) & biudata_valid;
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assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE) | (state == `OR1200_DCFSM_ILOAD) | (state == `OR1200_DCFSM_ISTORE)) & biudata_error;
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//
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//
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// Assert burst when doing reload of complete cache line
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// Assert burst when doing reload of complete cache line
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//
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//
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assign burst = (state == `OR1200_DCFSM_DOLOAD) & tagcomp_miss
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assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss
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| (state == `OR1200_DCFSM_LREFILL3) | (state == `OR1200_DCFSM_SREFILL4);
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| (state == `OR1200_DCFSM_LREFILL3)
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`ifdef OR1200_DC_STORE_REFILL
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| (state == `OR1200_DCFSM_SREFILL4)
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`endif
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;
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//
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//
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// Main DC FSM
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// Main DC FSM
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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| Line 169... |
Line 181... |
cnt <= #1 3'b000;
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cnt <= #1 3'b000;
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end
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end
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else
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else
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case (state) // synopsys parallel_case
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case (state) // synopsys parallel_case
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`OR1200_DCFSM_IDLE :
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`OR1200_DCFSM_IDLE :
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if (dc_en & dcdmmu_cyc_i & dcdmmu_stb_i & dcpu_we_i) begin // store
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if (dc_en & dcdmmu_ci_i & dcdmmu_cyc_i & dcdmmu_stb_i & dcpu_we_i) begin // store to cache-inhibited area
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state <= #1 `OR1200_DCFSM_DOSTORE;
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state <= #1 `OR1200_DCFSM_ISTORE;
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saved_addr <= #1 start_addr;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b1;
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load <= #1 1'b0;
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end
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else if (dc_en & dcdmmu_ci_i & dcdmmu_cyc_i & dcdmmu_stb_i) begin // load from cache-inhibited area
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state <= #1 `OR1200_DCFSM_ILOAD;
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saved_addr <= #1 start_addr;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b1;
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end
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else if (dc_en & dcdmmu_cyc_i & dcdmmu_stb_i & dcpu_we_i) begin // store to cached area
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state <= #1 `OR1200_DCFSM_CSTORE;
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saved_addr <= #1 start_addr;
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saved_addr <= #1 start_addr;
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hitmiss_eval <= #1 1'b1;
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hitmiss_eval <= #1 1'b1;
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store <= #1 1'b1;
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store <= #1 1'b1;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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else if (dc_en & dcdmmu_cyc_i & dcdmmu_stb_i) begin // load
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else if (dc_en & dcdmmu_cyc_i & dcdmmu_stb_i) begin // load from cached area
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state <= #1 `OR1200_DCFSM_DOLOAD;
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state <= #1 `OR1200_DCFSM_CLOAD;
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saved_addr <= #1 start_addr;
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saved_addr <= #1 start_addr;
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hitmiss_eval <= #1 1'b1;
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hitmiss_eval <= #1 1'b1;
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store <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b1;
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load <= #1 1'b1;
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end
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end
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| Line 189... |
Line 215... |
state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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`OR1200_DCFSM_DOLOAD:
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`OR1200_DCFSM_CLOAD: // load from cached area
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if (!dc_en)
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if (!dc_en)
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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else if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // load aborted (usually caused by DMMU)
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else if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // load aborted (usually caused by DMMU)
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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| Line 202... |
Line 228... |
else if (biudata_error) begin // load terminated with an error
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else if (biudata_error) begin // load terminated with an error
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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else if (dcdmmu_ci_i & biudata_valid) begin // load from cache inhibit page
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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end
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else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
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else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
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state <= #1 `OR1200_DCFSM_LREFILL3;
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state <= #1 `OR1200_DCFSM_LREFILL3;
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saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
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saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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cnt <= #1 `OR1200_DCLS-2;
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cnt <= #1 `OR1200_DCLS-2;
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end
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end
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else if (!tagcomp_miss & !dcdmmu_ci_i) begin // load hit and not cache inhibit, finish immediately
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else if (!tagcomp_miss) begin // load hit, finish immediately
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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else // load in-progress
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else // load in-progress
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| Line 232... |
Line 253... |
else if (biudata_valid) begin // last load of line refill
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else if (biudata_valid) begin // last load of line refill
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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end
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end
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`OR1200_DCFSM_DOSTORE:
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`OR1200_DCFSM_CSTORE: // store to cached area
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if (!dc_en)
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if (!dc_en)
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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else if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // store aborted (usually caused by DMMU)
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else if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // store aborted (usually caused by DMMU)
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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| Line 245... |
Line 266... |
else if (biudata_error) begin // store terminated with an error
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else if (biudata_error) begin // store terminated with an error
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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end
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end
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else if (dcdmmu_ci_i & biudata_valid) begin // store to cache inhibit page
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`ifdef OR1200_DC_STORE_REFILL
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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end
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else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and do load refill
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else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and do load refill
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state <= #1 `OR1200_DCFSM_SREFILL4;
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state <= #1 `OR1200_DCFSM_SREFILL4;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b1;
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load <= #1 1'b1;
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cnt <= #1 `OR1200_DCLS-1;
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cnt <= #1 `OR1200_DCLS-1;
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end
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end
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`endif
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else if (biudata_valid) begin // store hit, finish write-through
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else if (biudata_valid) begin // store hit, finish write-through
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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end
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end
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else // store write-through in-progress
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else // store write-through in-progress
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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`ifdef OR1200_DC_STORE_REFILL
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`OR1200_DCFSM_SREFILL4 : begin
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`OR1200_DCFSM_SREFILL4 : begin
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if (!dc_en)
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if (!dc_en)
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
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else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
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cnt <= #1 cnt - 'd1;
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cnt <= #1 cnt - 'd1;
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| Line 276... |
Line 295... |
else if (biudata_valid) begin // last load of line refill
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else if (biudata_valid) begin // last load of line refill
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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end
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end
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`endif
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`OR1200_DCFSM_ILOAD: // load from cache-inhibited area
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if (!dc_en)
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state <= #1 `OR1200_DCFSM_IDLE;
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else if (!(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // load aborted (usually caused by DMMU)
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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end
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else if (biudata_error) begin // load terminated with an error
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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end
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else if (biudata_valid) begin // load from cache inhibit page
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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end
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else // load in-progress
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hitmiss_eval <= #1 1'b0;
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`OR1200_DCFSM_ISTORE: // store to cache-inhibited area
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if (!dc_en)
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state <= #1 `OR1200_DCFSM_IDLE;
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else if (!(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // store aborted (usually caused by DMMU)
|
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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end
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else if (biudata_error) begin // store terminated with an error
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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end
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else if (biudata_valid) begin // store to cache inhibit page
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state <= #1 `OR1200_DCFSM_IDLE;
|
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
|
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end
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else // store write-through in-progress
|
|
hitmiss_eval <= #1 1'b0;
|
default:
|
default:
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
endcase
|
endcase
|
end
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end
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|
