| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.3 2002/01/28 01:15:59 lampret
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// Revision 1.3 2002/01/28 01:15:59 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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| Line 93... |
Line 96... |
module or1200_dc_fsm(
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module or1200_dc_fsm(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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|
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// Internal i/f to top level DC
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// Internal i/f to top level DC
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dc_en, dcdmmu_cyc_i, dcdmmu_stb_i, dcdmmu_ci_i, dcpu_we_i, dcpu_sel_i,
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dc_en, dcdmmu_cycstb_i, dcdmmu_ci_i, dcpu_we_i, dcpu_sel_i,
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tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
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tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
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dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
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dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
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burst
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burst, tag_we, dc_addr
|
);
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);
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|
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//
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//
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// I/O
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// I/O
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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input dc_en;
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input dc_en;
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input dcdmmu_cyc_i;
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input dcdmmu_cycstb_i;
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input dcdmmu_stb_i;
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input dcdmmu_ci_i;
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input dcdmmu_ci_i;
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input dcpu_we_i;
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input dcpu_we_i;
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input [3:0] dcpu_sel_i;
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input [3:0] dcpu_sel_i;
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input tagcomp_miss;
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input tagcomp_miss;
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input biudata_valid;
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input biudata_valid;
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| Line 122... |
Line 124... |
output biu_write;
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output biu_write;
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output first_hit_ack;
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output first_hit_ack;
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output first_miss_ack;
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output first_miss_ack;
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output first_miss_err;
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output first_miss_err;
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output burst;
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output burst;
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output tag_we;
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output [31:0] dc_addr;
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|
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [31:0] saved_addr;
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reg [31:0] saved_addr_r;
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reg [2:0] state;
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reg [2:0] state;
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reg [2:0] cnt;
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reg [2:0] cnt;
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reg hitmiss_eval;
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reg hitmiss_eval;
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reg store;
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reg store;
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reg load;
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reg load;
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reg cache_inhibit;
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wire first_store_hit_ack;
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wire first_store_hit_ack;
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|
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//
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//
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// Generate of DCRAM write enables
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// Generate of DCRAM write enables
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//
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//
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assign dcram_we = {4{load & biudata_valid & (state != `OR1200_DCFSM_ILOAD)}} | {4{first_store_hit_ack}} & dcpu_sel_i;
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assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcpu_sel_i;
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assign tag_we = biu_read & biudata_valid & !cache_inhibit;
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|
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//
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//
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// BIU read and write
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// BIU read and write
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//
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//
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assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
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assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
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assign biu_write = store;
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assign biu_write = store;
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|
|
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assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr;
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assign saved_addr = saved_addr_r;
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|
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//
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//
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// Assert for cache hit first word ready
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// Assert for cache hit first word ready
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// Assert for store cache hit first word ready
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// Assert for store cache hit first word ready
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded with an error
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// Assert for cache miss first word stored/loaded with an error
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//
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//
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assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss | first_store_hit_ack;
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assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcdmmu_ci_i | first_store_hit_ack;
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assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid;
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assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcdmmu_ci_i;
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assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE) | (state == `OR1200_DCFSM_ILOAD) | (state == `OR1200_DCFSM_ISTORE)) & biudata_valid;
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assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
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assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE) | (state == `OR1200_DCFSM_ILOAD) | (state == `OR1200_DCFSM_ISTORE)) & biudata_error;
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assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
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|
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//
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//
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// Assert burst when doing reload of complete cache line
|
// Assert burst when doing reload of complete cache line
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//
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//
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assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss
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assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
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| (state == `OR1200_DCFSM_LREFILL3)
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| (state == `OR1200_DCFSM_LREFILL3)
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`ifdef OR1200_DC_STORE_REFILL
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`ifdef OR1200_DC_STORE_REFILL
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| (state == `OR1200_DCFSM_SREFILL4)
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| (state == `OR1200_DCFSM_SREFILL4)
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`endif
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`endif
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;
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;
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| Line 172... |
Line 181... |
// Main DC FSM
|
// Main DC FSM
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
|
if (rst) begin
|
state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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saved_addr <= #1 32'b0;
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saved_addr_r <= #1 32'b0;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cnt <= #1 3'b000;
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cnt <= #1 3'b000;
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cache_inhibit <= #1 1'b0;
|
end
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end
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else
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else
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case (state) // synopsys parallel_case
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case (state) // synopsys parallel_case
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`OR1200_DCFSM_IDLE :
|
`OR1200_DCFSM_IDLE :
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if (dc_en & dcdmmu_ci_i & dcdmmu_cyc_i & dcdmmu_stb_i & dcpu_we_i) begin // store to cache-inhibited area
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if (dc_en & dcdmmu_cycstb_i & dcpu_we_i) begin // store
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state <= #1 `OR1200_DCFSM_ISTORE;
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saved_addr <= #1 start_addr;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b1;
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load <= #1 1'b0;
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end
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else if (dc_en & dcdmmu_ci_i & dcdmmu_cyc_i & dcdmmu_stb_i) begin // load from cache-inhibited area
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state <= #1 `OR1200_DCFSM_ILOAD;
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saved_addr <= #1 start_addr;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b1;
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end
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else if (dc_en & dcdmmu_cyc_i & dcdmmu_stb_i & dcpu_we_i) begin // store to cached area
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state <= #1 `OR1200_DCFSM_CSTORE;
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state <= #1 `OR1200_DCFSM_CSTORE;
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saved_addr <= #1 start_addr;
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saved_addr_r <= #1 start_addr;
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hitmiss_eval <= #1 1'b1;
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hitmiss_eval <= #1 1'b1;
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store <= #1 1'b1;
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store <= #1 1'b1;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else if (dc_en & dcdmmu_cyc_i & dcdmmu_stb_i) begin // load from cached area
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else if (dc_en & dcdmmu_cycstb_i) begin // load
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state <= #1 `OR1200_DCFSM_CLOAD;
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state <= #1 `OR1200_DCFSM_CLOAD;
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saved_addr <= #1 start_addr;
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saved_addr_r <= #1 start_addr;
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hitmiss_eval <= #1 1'b1;
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hitmiss_eval <= #1 1'b1;
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store <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b1;
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load <= #1 1'b1;
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cache_inhibit <= #1 1'b0;
|
end
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end
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else begin // idle
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else begin // idle
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
|
end
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`OR1200_DCFSM_CLOAD: // load from cached area
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`OR1200_DCFSM_CLOAD: begin // load
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if (dcdmmu_cycstb_i & dcdmmu_ci_i)
|
|
cache_inhibit <= #1 1'b1;
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if (hitmiss_eval)
|
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saved_addr_r[31:13] <= #1 start_addr[31:13];
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if (!dc_en)
|
if (!dc_en)
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
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else if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // load aborted (usually caused by DMMU)
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else if (hitmiss_eval & !dcdmmu_cycstb_i) begin // load aborted (usually caused by DMMU)
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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|
cache_inhibit <= #1 1'b0;
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end
|
end
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else if (biudata_error) begin // load terminated with an error
|
else if (biudata_error) begin // load terminated with an error
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
|
cache_inhibit <= #1 1'b0;
|
|
end
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else if ((cache_inhibit | dcdmmu_ci_i) & biudata_valid) begin // load from cache-inhibited area
|
|
state <= #1 `OR1200_DCFSM_IDLE;
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|
hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
|
else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
|
state <= #1 `OR1200_DCFSM_LREFILL3;
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state <= #1 `OR1200_DCFSM_LREFILL3;
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saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
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hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
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cnt <= #1 `OR1200_DCLS-2;
|
cnt <= #1 `OR1200_DCLS-2;
|
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else if (!tagcomp_miss) begin // load hit, finish immediately
|
else if (!tagcomp_miss & !dcdmmu_ci_i) begin // load hit, finish immediately
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else // load in-progress
|
else // load in-progress
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
|
end
|
`OR1200_DCFSM_LREFILL3 : begin
|
`OR1200_DCFSM_LREFILL3 : begin
|
if (!dc_en)
|
if (!dc_en)
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
cnt <= #1 cnt - 'd1;
|
cnt <= #1 cnt - 'd1;
|
saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
|
end
|
end
|
else if (biudata_valid) begin // last load of line refill
|
else if (biudata_valid) begin // last load of line refill
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
end
|
end
|
end
|
end
|
`OR1200_DCFSM_CSTORE: // store to cached area
|
`OR1200_DCFSM_CSTORE: begin // store
|
|
if (dcdmmu_cycstb_i & dcdmmu_ci_i)
|
|
cache_inhibit <= #1 1'b1;
|
|
if (hitmiss_eval)
|
|
saved_addr_r[31:13] <= #1 start_addr[31:13];
|
if (!dc_en)
|
if (!dc_en)
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
else if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // store aborted (usually caused by DMMU)
|
else if (hitmiss_eval & !dcdmmu_cycstb_i) begin // store aborted (usually caused by DMMU)
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else if (biudata_error) begin // store terminated with an error
|
else if (biudata_error) begin // store terminated with an error
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
|
cache_inhibit <= #1 1'b0;
|
|
end
|
|
else if ((cache_inhibit | dcdmmu_ci_i) & biudata_valid) begin // store to cache-inhibited area
|
|
state <= #1 `OR1200_DCFSM_IDLE;
|
|
hitmiss_eval <= #1 1'b0;
|
|
store <= #1 1'b0;
|
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
`ifdef OR1200_DC_STORE_REFILL
|
`ifdef OR1200_DC_STORE_REFILL
|
else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and do load refill
|
else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and do load refill
|
state <= #1 `OR1200_DCFSM_SREFILL4;
|
state <= #1 `OR1200_DCFSM_SREFILL4;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
load <= #1 1'b1;
|
load <= #1 1'b1;
|
cnt <= #1 `OR1200_DCLS-1;
|
cnt <= #1 `OR1200_DCLS-1;
|
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
`endif
|
`endif
|
else if (biudata_valid) begin // store hit, finish write-through
|
else if (biudata_valid) begin // store hit, finish write-through
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
|
cache_inhibit <= #1 1'b0;
|
end
|
end
|
else // store write-through in-progress
|
else // store write-through in-progress
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
|
end
|
`ifdef OR1200_DC_STORE_REFILL
|
`ifdef OR1200_DC_STORE_REFILL
|
`OR1200_DCFSM_SREFILL4 : begin
|
`OR1200_DCFSM_SREFILL4 : begin
|
if (!dc_en)
|
if (!dc_en)
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
cnt <= #1 cnt - 'd1;
|
cnt <= #1 cnt - 'd1;
|
saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
|
end
|
end
|
else if (biudata_valid) begin // last load of line refill
|
else if (biudata_valid) begin // last load of line refill
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
end
|
end
|
end
|
end
|
`endif
|
`endif
|
`OR1200_DCFSM_ILOAD: // load from cache-inhibited area
|
|
if (!dc_en)
|
|
state <= #1 `OR1200_DCFSM_IDLE;
|
|
else if (!(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // load aborted (usually caused by DMMU)
|
|
state <= #1 `OR1200_DCFSM_IDLE;
|
|
hitmiss_eval <= #1 1'b0;
|
|
load <= #1 1'b0;
|
|
end
|
|
else if (biudata_error) begin // load terminated with an error
|
|
state <= #1 `OR1200_DCFSM_IDLE;
|
|
hitmiss_eval <= #1 1'b0;
|
|
load <= #1 1'b0;
|
|
end
|
|
else if (biudata_valid) begin // load from cache inhibit page
|
|
state <= #1 `OR1200_DCFSM_IDLE;
|
|
hitmiss_eval <= #1 1'b0;
|
|
load <= #1 1'b0;
|
|
end
|
|
else // load in-progress
|
|
hitmiss_eval <= #1 1'b0;
|
|
`OR1200_DCFSM_ISTORE: // store to cache-inhibited area
|
|
if (!dc_en)
|
|
state <= #1 `OR1200_DCFSM_IDLE;
|
|
else if (!(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // store aborted (usually caused by DMMU)
|
|
state <= #1 `OR1200_DCFSM_IDLE;
|
|
hitmiss_eval <= #1 1'b0;
|
|
store <= #1 1'b0;
|
|
end
|
|
else if (biudata_error) begin // store terminated with an error
|
|
state <= #1 `OR1200_DCFSM_IDLE;
|
|
hitmiss_eval <= #1 1'b0;
|
|
store <= #1 1'b0;
|
|
end
|
|
else if (biudata_valid) begin // store to cache inhibit page
|
|
state <= #1 `OR1200_DCFSM_IDLE;
|
|
hitmiss_eval <= #1 1'b0;
|
|
store <= #1 1'b0;
|
|
end
|
|
else // store write-through in-progress
|
|
hitmiss_eval <= #1 1'b0;
|
|
default:
|
default:
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
endcase
|
endcase
|
end
|
end
|
|
|
