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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 778 and 788

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Rev 778	Rev 788
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.12 2002/03/28 19:25:42 lampret`
	`// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.`
	`//`
`// Revision 1.11 2002/03/28 19:13:17 lampret`	`// Revision 1.11 2002/03/28 19:13:17 lampret`
`// Updated defines.`	`// Updated defines.`
`//`	`//`
`// Revision 1.10 2002/03/14 00:30:24 lampret`	`// Revision 1.10 2002/03/14 00:30:24 lampret`
`// Added alternative for critical path in DU.`	`// Added alternative for critical path in DU.`
Line 276...	Line 279...
`//////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////`
`//`	`//`
`// Do not change below unless you know what you are doing`	`// Do not change below unless you know what you are doing`
`//`	`//`

	`//`
	`// Enable additional synthesis directives if using`
	`// Synopsys synthesis tool`
	`//`
	//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES

	`//`
`// Operand width / register file address width`	`// Operand width / register file address width`
	`//`
	`// (DO NOT CHANGE)`
	`//`
`define OR1200_OPERAND_WIDTH 32	`define OR1200_OPERAND_WIDTH 32
`define OR1200_REGFILE_ADDR_WIDTH 5	`define OR1200_REGFILE_ADDR_WIDTH 5

`//`	`//`
`// Implement rotate in the ALU`	`// Implement rotate in the ALU`

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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 778 and 788