| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
|
//
|
// Revision 1.8 2001/10/21 17:57:16 lampret
|
// Revision 1.8 2001/10/21 17:57:16 lampret
|
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
|
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
|
//
|
//
|
// Revision 1.7 2001/10/14 13:12:09 lampret
|
// Revision 1.7 2001/10/14 13:12:09 lampret
|
// MP3 version.
|
// MP3 version.
|
| Line 67... |
Line 70... |
module or1200_dmmu_tlb(
|
module or1200_dmmu_tlb(
|
// Rst and clk
|
// Rst and clk
|
clk, rst,
|
clk, rst,
|
|
|
// I/F for translation
|
// I/F for translation
|
tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci, done,
|
tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,
|
|
|
// SPR access
|
// SPR access
|
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
|
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
|
);
|
);
|
|
|
| Line 98... |
Line 101... |
output uwe;
|
output uwe;
|
output ure;
|
output ure;
|
output swe;
|
output swe;
|
output sre;
|
output sre;
|
output ci;
|
output ci;
|
output done;
|
|
|
|
//
|
//
|
// SPR access
|
// SPR access
|
//
|
//
|
input spr_cs;
|
input spr_cs;
|
| Line 123... |
Line 125... |
wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_out;
|
wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_out;
|
wire tlb_tr_en;
|
wire tlb_tr_en;
|
wire tlb_tr_we;
|
wire tlb_tr_we;
|
wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_in;
|
wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_in;
|
wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out;
|
wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out;
|
reg done;
|
|
|
|
//
|
//
|
// Implemented bits inside match and translate registers
|
// Implemented bits inside match and translate registers
|
//
|
//
|
// dtlbwYmrX: vpn 31-19 v 0
|
// dtlbwYmrX: vpn 31-19 v 0
|
| Line 162... |
Line 163... |
|
|
//
|
//
|
// Output to SPRS unit
|
// Output to SPRS unit
|
//
|
//
|
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]) ?
|
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]) ?
|
{vpn, {`OR1200_DTLB_INDXH{1'b1}}, v} :
|
{vpn, tlb_index, {`OR1200_DTLB_TAGW-1{1'b0}}, v} :
|
(spr_cs & !spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]) ?
|
(spr_cs & !spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]) ?
|
{ppn, {`OR1200_DMMU_PS-10{1'b0}}, swe, sre, uwe, ure, {5{1'b1}}, ci} :
|
{ppn, {`OR1200_DMMU_PS-10{1'b0}}, swe, sre, uwe, ure, {4{1'b0}}, ci, 1'b0} :
|
32'h00000000;
|
32'h00000000;
|
|
|
//
|
//
|
// Assign outputs from Match registers
|
// Assign outputs from Match registers
|
//
|
//
|
| Line 204... |
Line 205... |
// spr_addr[5:0].
|
// spr_addr[5:0].
|
//
|
//
|
assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] : vaddr[`OR1200_DTLB_INDX];
|
assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] : vaddr[`OR1200_DTLB_INDX];
|
|
|
//
|
//
|
// Assert one clock cycle after tlb_en is asserted. Deassert once tlb_en is
|
|
// deasserted.
|
|
//
|
|
always @(posedge clk or posedge rst)
|
|
if (rst)
|
|
done <= #1 1'b0;
|
|
else if (tlb_en)
|
|
done <= #1 1'b1;
|
|
else
|
|
done <= #1 1'b0;
|
|
|
|
//
|
|
// Instantiation of DTLB Match Registers
|
// Instantiation of DTLB Match Registers
|
//
|
//
|
or1200_spram_64x14 dtlb_mr_ram(
|
or1200_spram_64x14 dtlb_mr_ram(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
