| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/03/29 15:16:55 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.5 2002/02/14 15:34:02 simons
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// Revision 1.5 2002/02/14 15:34:02 simons
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// Lapsus fixed.
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// Lapsus fixed.
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//
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//
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// Revision 1.4 2002/02/11 04:33:17 lampret
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// Revision 1.4 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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| Line 97... |
Line 100... |
dcpu_tag_o, dcpu_err_o,
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dcpu_tag_o, dcpu_err_o,
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// SPR access
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// SPR access
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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`ifdef OR1200_BIST
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// RAM BIST
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scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
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`endif
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// DC i/f
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// DC i/f
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dcdmmu_err_i, dcdmmu_tag_i, dcdmmu_adr_o, dcdmmu_cycstb_o, dcdmmu_ci_o
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dcdmmu_err_i, dcdmmu_tag_i, dcdmmu_adr_o, dcdmmu_cycstb_o, dcdmmu_ci_o
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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| Line 135... |
Line 143... |
input spr_write;
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input spr_write;
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input [aw-1:0] spr_addr;
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input [aw-1:0] spr_addr;
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input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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output [31:0] spr_dat_o;
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output [31:0] spr_dat_o;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input scanb_rst,
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scanb_si,
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scanb_en,
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scanb_clk;
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output scanb_so;
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`endif
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//
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//
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// DC I/F
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// DC I/F
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//
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//
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input dcdmmu_err_i;
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input dcdmmu_err_i;
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input [3:0] dcdmmu_tag_i;
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input [3:0] dcdmmu_tag_i;
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| Line 189... |
Line 208... |
assign dcdmmu_adr_o = dcpu_adr_i;
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assign dcdmmu_adr_o = dcpu_adr_i;
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assign dcpu_tag_o = dcdmmu_tag_i;
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assign dcpu_tag_o = dcdmmu_tag_i;
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assign dcdmmu_cycstb_o = dcpu_cycstb_i;
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assign dcdmmu_cycstb_o = dcpu_cycstb_i;
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assign dcpu_err_o = dcdmmu_err_i;
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assign dcpu_err_o = dcdmmu_err_i;
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assign dcdmmu_ci_o = `OR1200_DMMU_CI;
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assign dcdmmu_ci_o = `OR1200_DMMU_CI;
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`ifdef OR1200_BIST
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assign scanb_so = scanb_si;
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`endif
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`else
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`else
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//
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//
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// DTLB SPR access
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// DTLB SPR access
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| Line 298... |
Line 320... |
.ure(dtlb_ure),
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.ure(dtlb_ure),
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.swe(dtlb_swe),
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.swe(dtlb_swe),
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.sre(dtlb_sre),
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.sre(dtlb_sre),
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.ci(dtlb_ci),
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.ci(dtlb_ci),
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`ifdef OR1200_BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_si),
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.scanb_so(scanb_so),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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// SPR access
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// SPR access
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.spr_cs(dtlb_spr_access),
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.spr_cs(dtlb_spr_access),
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.spr_write(spr_write),
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.spr_write(spr_write),
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.spr_addr(spr_addr),
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.spr_addr(spr_addr),
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.spr_dat_i(spr_dat_i),
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.spr_dat_i(spr_dat_i),
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