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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/01/23 07:52:36 lampret
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// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
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//
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// Revision 1.3 2002/01/19 14:10:22 lampret
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// Revision 1.3 2002/01/19 14:10:22 lampret
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// Fixed OR1200_XILINX_RAM32X1D.
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// Fixed OR1200_XILINX_RAM32X1D.
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//
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//
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// Revision 1.2 2002/01/15 06:12:22 lampret
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// Revision 1.2 2002/01/15 06:12:22 lampret
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// Fixed module name when compiling with OR1200_XILINX_RAM32X1D
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// Fixed module name when compiling with OR1200_XILINX_RAM32X1D
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// Instantiation of ASIC memory:
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// Instantiation of ASIC memory:
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//
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//
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// Virtual Silicon Two-port R/W SRAM
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// Virtual Silicon Two-port R/W SRAM
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//
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//
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`ifdef UNUSED
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`ifdef UNUSED
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vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(
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vs_hdtp_64x32 #(1<<aw, aw-1, dw-1) vs_ssp(
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`else
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`else
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vs_hdtp_32x32 vs_ssp(
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vs_hdtp_64x32 vs_ssp(
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`endif
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`endif
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.RCK(clk_a),
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.P1CK(clk_a),
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.REN(~ce_a),
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.P1CEN(~ce_a),
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.OEN(~oe_a),
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.P1WEN(1'b1),
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.RADR(addr_a),
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.P1OEN(~oe_a),
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.DI(di_b),
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.P1ADR({1'b0, addr_a}),
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.WCK(clk_b),
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.P1DI(32'h0000_0000),
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.WEN(~ce_b),
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.P1DOUT(do_a),
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.WADR(addr_b),
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.DOUT(do_a)
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.P2CK(clk_b),
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.P2CEN(~ce_b),
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.P2WEN(~ce_b),
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.P2OEN(1'b1),
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.P2ADR({1'b0, addr_b}),
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.P2DI(di_b),
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.P2DOUT()
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);
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);
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`else
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`else
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`ifdef OR1200_XILINX_RAM32X1D
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`ifdef OR1200_XILINX_RAM32X1D
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