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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.14 2002/09/03 22:28:21 lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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//
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// Revision 1.13 2002/08/28 01:44:25 lampret
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// Revision 1.13 2002/08/28 01:44:25 lampret
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// Removed some commented RTL. Fixed SR/ESR flag bug.
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// Removed some commented RTL. Fixed SR/ESR flag bug.
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//
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//
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// Revision 1.12 2002/08/22 02:16:45 lampret
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// Revision 1.12 2002/08/22 02:16:45 lampret
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// Fixed IMMU bug.
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// Fixed IMMU bug.
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| Line 412... |
Line 415... |
if (except_flushpipe) begin
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if (except_flushpipe) begin
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state <= #1 `OR1200_EXCEPTFSM_FLU1;
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state <= #1 `OR1200_EXCEPTFSM_FLU1;
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extend_flush <= #1 1'b1;
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extend_flush <= #1 1'b1;
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esr <= #1 sr_we ? to_sr : sr;
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esr <= #1 sr_we ? to_sr : sr;
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casex (except_trig)
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casex (except_trig)
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`ifdef OR1200_EXCEPT_TICK
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13'b1_xxxx_xxxx_xxxx: begin
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13'b1_xxxx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_TICK;
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except_type <= #1 `OR1200_EXCEPT_TICK;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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`endif
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`ifdef OR1200_EXCEPT_INT
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13'b0_1xxx_xxxx_xxxx: begin
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13'b0_1xxx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_INT;
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except_type <= #1 `OR1200_EXCEPT_INT;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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`endif
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`ifdef OR1200_EXCEPT_ITLBMISS
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13'b0_01xx_xxxx_xxxx: begin
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13'b0_01xx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
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except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
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//
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//
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// itlb miss exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?)
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// itlb miss exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?)
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// eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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// eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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Line 440... |
eear <= #1 ex_dslot ? ex_pc : ex_pc;
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eear <= #1 ex_dslot ? ex_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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// eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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// eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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// epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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// epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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`endif
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`ifdef OR1200_EXCEPT_IPF
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13'b0_001x_xxxx_xxxx: begin
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13'b0_001x_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_IPF;
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except_type <= #1 `OR1200_EXCEPT_IPF;
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//
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//
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// ipf exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?)
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// ipf exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?)
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// eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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// eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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`endif
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`ifdef OR1200_EXCEPT_BUSERR
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13'b0_0001_xxxx_xxxx: begin
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13'b0_0001_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_BUSERR;
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except_type <= #1 `OR1200_EXCEPT_BUSERR;
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eear <= #1 ex_dslot ? wb_pc : ex_pc;
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eear <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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`endif
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`ifdef OR1200_EXCEPT_ILLEGAL
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13'b0_0000_1xxx_xxxx: begin
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13'b0_0000_1xxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
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except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
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eear <= #1 ex_pc;
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eear <= #1 ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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`endif
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`ifdef OR1200_EXCEPT_ALIGN
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13'b0_0000_01xx_xxxx: begin
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13'b0_0000_01xx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_ALIGN;
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except_type <= #1 `OR1200_EXCEPT_ALIGN;
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eear <= #1 lsu_addr;
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eear <= #1 lsu_addr;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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`endif
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`ifdef OR1200_EXCEPT_DTLBMISS
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13'b0_0000_001x_xxxx: begin
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13'b0_0000_001x_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
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except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
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eear <= #1 lsu_addr;
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eear <= #1 lsu_addr;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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`endif
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`ifdef OR1200_EXCEPT_DPF
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13'b0_0000_0001_xxxx: begin
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13'b0_0000_0001_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_DPF;
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except_type <= #1 `OR1200_EXCEPT_DPF;
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eear <= #1 lsu_addr;
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eear <= #1 lsu_addr;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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`endif
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`ifdef OR1200_EXCEPT_BUSERR
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13'b0_0000_0000_1xxx: begin // Data Bus Error
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13'b0_0000_0000_1xxx: begin // Data Bus Error
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except_type <= #1 `OR1200_EXCEPT_BUSERR;
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except_type <= #1 `OR1200_EXCEPT_BUSERR;
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eear <= #1 lsu_addr;
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eear <= #1 lsu_addr;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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`endif
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`ifdef OR1200_EXCEPT_RANGE
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13'b0_0000_0000_01xx: begin
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13'b0_0000_0000_01xx: begin
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except_type <= #1 `OR1200_EXCEPT_RANGE;
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except_type <= #1 `OR1200_EXCEPT_RANGE;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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13'b0_0000_0000_001x: begin
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`endif
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`ifdef OR1200_EXCEPT_TRAP 13'b0_0000_0000_001x: begin
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except_type <= #1 `OR1200_EXCEPT_TRAP;
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except_type <= #1 `OR1200_EXCEPT_TRAP;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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`endif
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`ifdef OR1200_EXCEPT_SYSCALL
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13'b0_0000_0000_0001: begin
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13'b0_0000_0000_0001: begin
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except_type <= #1 `OR1200_EXCEPT_SYSCALL;
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except_type <= #1 `OR1200_EXCEPT_SYSCALL;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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`endif
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default:
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default:
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except_type <= #1 `OR1200_EXCEPT_NONE;
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except_type <= #1 `OR1200_EXCEPT_NONE;
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endcase
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endcase
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end
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end
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else if (pc_we) begin
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else if (pc_we) begin
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| Line 502... |
Line 530... |
end
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end
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`OR1200_EXCEPTFSM_FLU1:
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`OR1200_EXCEPTFSM_FLU1:
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if (icpu_ack_i | icpu_err_i | genpc_freeze)
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if (icpu_ack_i | icpu_err_i | genpc_freeze)
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state <= #1 `OR1200_EXCEPTFSM_FLU2;
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state <= #1 `OR1200_EXCEPTFSM_FLU2;
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`OR1200_EXCEPTFSM_FLU2:
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`OR1200_EXCEPTFSM_FLU2:
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`ifdef OR1200_EXCEPT_TRAP
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if (except_type == `OR1200_EXCEPT_TRAP) begin
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if (except_type == `OR1200_EXCEPT_TRAP) begin
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state <= #1 `OR1200_EXCEPTFSM_IDLE;
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state <= #1 `OR1200_EXCEPTFSM_IDLE;
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extend_flush <= #1 1'b0;
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extend_flush <= #1 1'b0;
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extend_flush_last <= #1 1'b0;
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extend_flush_last <= #1 1'b0;
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except_type <= #1 `OR1200_EXCEPT_NONE;
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except_type <= #1 `OR1200_EXCEPT_NONE;
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end
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end
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else
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else
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`endif
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state <= #1 `OR1200_EXCEPTFSM_FLU3;
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state <= #1 `OR1200_EXCEPTFSM_FLU3;
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`OR1200_EXCEPTFSM_FLU3:
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`OR1200_EXCEPTFSM_FLU3:
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begin
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begin
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state <= #1 `OR1200_EXCEPTFSM_FLU4;
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state <= #1 `OR1200_EXCEPTFSM_FLU4;
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end
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end
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