| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.5 2002/02/11 04:33:17 lampret
|
|
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
|
|
//
|
// Revision 1.4 2002/01/28 01:16:00 lampret
|
// Revision 1.4 2002/01/28 01:16:00 lampret
|
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
|
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
|
//
|
//
|
// Revision 1.3 2002/01/18 07:56:00 lampret
|
// Revision 1.3 2002/01/18 07:56:00 lampret
|
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
|
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
|
| Line 88... |
Line 91... |
// Clock and reset
|
// Clock and reset
|
clk, rst,
|
clk, rst,
|
|
|
// External i/f to IC
|
// External i/f to IC
|
icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
|
icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
|
icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,
|
icpu_rty_i, icpu_adr_i,
|
|
|
// Internal i/f
|
// Internal i/f
|
branch_op, except_type, except_prefix,
|
branch_op, except_type, except_prefix,
|
branch_addrofs, lr_restor, flag, taken, except_start,
|
branch_addrofs, lr_restor, flag, taken, except_start,
|
binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
|
binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
|
genpc_freeze, flushpipe, no_more_dslot
|
genpc_freeze, no_more_dslot
|
);
|
);
|
|
|
//
|
//
|
// I/O
|
// I/O
|
//
|
//
|
| Line 114... |
Line 117... |
//
|
//
|
output [31:0] icpu_adr_o;
|
output [31:0] icpu_adr_o;
|
output icpu_cycstb_o;
|
output icpu_cycstb_o;
|
output [3:0] icpu_sel_o;
|
output [3:0] icpu_sel_o;
|
output [3:0] icpu_tag_o;
|
output [3:0] icpu_tag_o;
|
input icpu_ack_i;
|
|
input icpu_rty_i;
|
input icpu_rty_i;
|
input icpu_err_i;
|
|
input [31:0] icpu_adr_i;
|
input [31:0] icpu_adr_i;
|
|
|
//
|
//
|
// Internal i/f
|
// Internal i/f
|
//
|
//
|
| Line 136... |
Line 137... |
input [31:0] epcr;
|
input [31:0] epcr;
|
input [31:0] spr_dat_i;
|
input [31:0] spr_dat_i;
|
input spr_pc_we;
|
input spr_pc_we;
|
input genpc_refetch;
|
input genpc_refetch;
|
input genpc_freeze;
|
input genpc_freeze;
|
input flushpipe;
|
|
input no_more_dslot;
|
input no_more_dslot;
|
|
|
//
|
//
|
// Internal wires and regs
|
// Internal wires and regs
|
//
|
//
|
reg [31:2] pcreg;
|
reg [31:2] pcreg;
|
reg [31:0] pc;
|
reg [31:0] pc;
|
reg taken; /* Set to in case of jump or taken branch */
|
reg taken; /* Set to in case of jump or taken branch */
|
reg dslot; /* set when fetching delay slot insn */
|
|
reg btarget; /* set when fetching branch target insns */
|
|
|
|
//
|
//
|
// Address of insn to be fecthed
|
// Address of insn to be fecthed
|
//
|
//
|
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
|
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
|
