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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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Line 77... |
`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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`define OR1200_ICFSM_IDLE 3'd0
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`define OR1200_ICFSM_IDLE 3'd0
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`define OR1200_ICFSM_DOLOAD 3'd1
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`define OR1200_ICFSM_CFETCH 3'd1
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`define OR1200_ICFSM_LREFILL3 3'd2
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`define OR1200_ICFSM_LREFILL3 3'd2
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`define OR1200_ICFSM_IFETCH 3'd3
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//
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//
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// Data cache FSM for cache line of 16 bytes (4x singleword)
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// Data cache FSM for cache line of 16 bytes (4x singleword)
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//
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//
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Line 130... |
reg load;
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reg load;
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//
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//
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// Generate of ICRAM write enables
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// Generate of ICRAM write enables
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//
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//
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assign icram_we = {4{load & biudata_valid}};
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assign icram_we = {4{load & biudata_valid & (state != `OR1200_ICFSM_IFETCH)}};
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//
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//
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// BIU read and write
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// BIU read and write
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//
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//
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assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
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assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
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Line 142... |
//
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//
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// Assert for cache hit first word ready
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// Assert for cache hit first word ready
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded with an error
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// Assert for cache miss first word stored/loaded with an error
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//
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//
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assign first_hit_ack = (state == `OR1200_ICFSM_DOLOAD) & hitmiss_eval & !tagcomp_miss & !icimmu_ci_i;
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assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss;
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assign first_miss_ack = (state == `OR1200_ICFSM_DOLOAD) & (tagcomp_miss | icimmu_ci_i) & biudata_valid;
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assign first_miss_ack = ((state == `OR1200_ICFSM_CFETCH) | (state == `OR1200_ICFSM_IFETCH)) & biudata_valid;
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assign first_miss_err = (state == `OR1200_ICFSM_DOLOAD) & (tagcomp_miss | icimmu_ci_i) & biudata_error;
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assign first_miss_err = ((state == `OR1200_ICFSM_CFETCH) | (state == `OR1200_ICFSM_IFETCH)) & biudata_error;
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//
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//
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// Assert burst when doing reload of complete cache line
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// Assert burst when doing reload of complete cache line
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//
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//
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assign burst = (state == `OR1200_ICFSM_DOLOAD) & tagcomp_miss
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assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss
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| (state == `OR1200_ICFSM_LREFILL3);
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| (state == `OR1200_ICFSM_LREFILL3);
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//
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//
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// Main IC FSM
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// Main IC FSM
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//
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//
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Line 166... |
cnt <= #1 3'b000;
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cnt <= #1 3'b000;
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end
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end
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else
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else
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case (state) // synopsys parallel_case
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case (state) // synopsys parallel_case
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`OR1200_ICFSM_IDLE :
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`OR1200_ICFSM_IDLE :
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if (ic_en & icimmu_cyc_i & icimmu_stb_i) begin // load
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if (ic_en & icimmu_cyc_i & icimmu_stb_i & icimmu_ci_i) begin // fetch from cache-inhibited area
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state <= #1 `OR1200_ICFSM_DOLOAD;
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state <= #1 `OR1200_ICFSM_IFETCH;
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saved_addr <= #1 start_addr;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b1;
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end
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else if (ic_en & icimmu_cyc_i & icimmu_stb_i) begin // fetch from cached area
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state <= #1 `OR1200_ICFSM_CFETCH;
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saved_addr <= #1 start_addr;
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saved_addr <= #1 start_addr;
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hitmiss_eval <= #1 1'b1;
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hitmiss_eval <= #1 1'b1;
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load <= #1 1'b1;
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load <= #1 1'b1;
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end
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end
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else begin // idle
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else begin // idle
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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`OR1200_ICFSM_DOLOAD:
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`OR1200_ICFSM_CFETCH: // fetch from cached area
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if (!ic_en)
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if (!ic_en)
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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else if (hitmiss_eval & !(icimmu_cyc_i & icimmu_stb_i)) begin // load aborted (usually caused by IMMU)
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else if (hitmiss_eval & !(icimmu_cyc_i & icimmu_stb_i)) begin // fetch aborted (usually caused by IMMU)
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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else if (icimmu_ci_i & biudata_valid) begin // load from cache inhibit page
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else if (biudata_error) begin // fetch terminated with an error
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
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else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill
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state <= #1 `OR1200_ICFSM_LREFILL3;
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state <= #1 `OR1200_ICFSM_LREFILL3;
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saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
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saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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cnt <= #1 `OR1200_ICLS-2;
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cnt <= #1 `OR1200_ICLS-2;
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end
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end
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else if (!tagcomp_miss & !icimmu_ci_i) begin // load hit and not cache inhibit, finish immediately
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else if (!tagcomp_miss) begin // fetch hit, finish immediately
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state <= #1 `OR1200_ICFSM_DOLOAD;
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state <= #1 `OR1200_ICFSM_CFETCH;
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saved_addr <= #1 start_addr;
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saved_addr <= #1 start_addr;
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hitmiss_eval <= #1 1'b1;
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hitmiss_eval <= #1 1'b1;
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load <= #1 1'b1;
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load <= #1 1'b1;
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end
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end
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else if (!icimmu_cyc_i | !icimmu_stb_i) begin // load aborted (usually caused by exception)
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else if (!icimmu_cyc_i | !icimmu_stb_i) begin // fetch aborted (usually caused by exception)
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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else // load in-progress
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else // fetch in-progress
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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`OR1200_ICFSM_LREFILL3 : begin
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`OR1200_ICFSM_LREFILL3 : begin
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if (!ic_en)
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if (!ic_en)
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
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else if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
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cnt <= #1 cnt - 'd1;
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cnt <= #1 cnt - 'd1;
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saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
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saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
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end
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end
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else if (biudata_valid) begin // last load of line refill
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else if (biudata_valid) begin // last fetch of line refill
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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saved_addr <= #1 start_addr;
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saved_addr <= #1 start_addr;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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end
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end
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`OR1200_ICFSM_IFETCH: // fetch from cache-inhibited area
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if (!ic_en)
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state <= #1 `OR1200_ICFSM_IDLE;
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else if (!(icimmu_cyc_i & icimmu_stb_i)) begin // fetch aborted (usually caused by IMMU)
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state <= #1 `OR1200_ICFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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end
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else if (biudata_error) begin // fetch terminated with an error
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state <= #1 `OR1200_ICFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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end
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else if (biudata_valid) begin // fetch from cache inhibit page
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state <= #1 `OR1200_ICFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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end
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else // fetch in-progress
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hitmiss_eval <= #1 1'b0;
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default:
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default:
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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endcase
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endcase
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end
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end
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