| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
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| Line 88... |
Line 91... |
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// Internal i/f
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// Internal i/f
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ic_en,
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ic_en,
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icimmu_adr_i, icimmu_cyc_i, icimmu_stb_i, icimmu_ci_i,
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icimmu_adr_i, icimmu_cyc_i, icimmu_stb_i, icimmu_ci_i,
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icpu_we_i, icpu_sel_i, icpu_tag_i,
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icpu_we_i, icpu_sel_i, icpu_tag_i,
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icpu_dat_o, icpu_ack_o, icpu_rty_o, icimmu_err_o, icimmu_tag_o,
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icpu_dat_o, icpu_ack_o, icimmu_rty_o, icimmu_err_o, icimmu_tag_o,
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// SPRs
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// SPRs
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spr_cs, spr_write, spr_dat_i
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spr_cs, spr_write, spr_dat_i
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);
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);
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| Line 133... |
Line 136... |
input icpu_we_i;
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input icpu_we_i;
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input [3:0] icpu_sel_i;
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input [3:0] icpu_sel_i;
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input [3:0] icpu_tag_i;
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input [3:0] icpu_tag_i;
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output [dw-1:0] icpu_dat_o;
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output [dw-1:0] icpu_dat_o;
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output icpu_ack_o;
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output icpu_ack_o;
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output icpu_rty_o;
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output icimmu_rty_o;
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output icimmu_err_o;
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output icimmu_err_o;
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output [3:0] icimmu_tag_o;
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output [3:0] icimmu_tag_o;
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//
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//
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// SPR access
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// SPR access
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| Line 190... |
Line 193... |
assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icimmu_cyc_i;
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assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icimmu_cyc_i;
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assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icimmu_stb_i;
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assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icimmu_stb_i;
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assign icbiu_we_o = 1'b0;
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assign icbiu_we_o = 1'b0;
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assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icpu_sel_i;
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assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icpu_sel_i;
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assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
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assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
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assign icpu_rty_o = ~icpu_ack_o;
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assign icimmu_rty_o = ~icpu_ack_o & ~icimmu_err_o;
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assign icimmu_tag_o = icimmu_err_o ? `OR1200_ITAG_BE : icpu_tag_i;
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assign icimmu_tag_o = icimmu_err_o ? `OR1200_ITAG_BE : icpu_tag_i;
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//
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//
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// CPU normal and error termination
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// CPU normal and error termination
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//
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//
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assign icpu_ack_o = ic_en ? icfsm_first_hit_ack | icfsm_first_miss_ack : icbiu_ack_i;
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// assign icpu_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) & !ic_inv : icbiu_ack_i;
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assign icpu_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
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assign icimmu_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
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assign icimmu_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
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//
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//
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// Select between claddr generated by IC FSM and addr[3:2] generated by LSU
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// Select between claddr generated by IC FSM and addr[3:2] generated by LSU
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//
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//
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