| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2002/09/16 03:08:56 lampret
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// Disabled cache inhibit atttribute.
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//
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// Revision 1.9 2002/08/18 19:54:17 lampret
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// Revision 1.9 2002/08/18 19:54:17 lampret
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// Added store buffer.
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// Added store buffer.
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//
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//
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// Revision 1.8 2002/08/14 06:23:50 lampret
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// Revision 1.8 2002/08/14 06:23:50 lampret
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// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
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// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
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| Line 109... |
Line 112... |
icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
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icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
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// SPR access
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// SPR access
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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`ifdef OR1200_BIST
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// RAM BIST
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scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
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`endif
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// IC i/f
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// IC i/f
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icimmu_rty_i, icimmu_err_i, icimmu_tag_i, icimmu_adr_o, icimmu_cycstb_o, icimmu_ci_o
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icimmu_rty_i, icimmu_err_i, icimmu_tag_i, icimmu_adr_o, icimmu_cycstb_o, icimmu_ci_o
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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| Line 148... |
Line 156... |
input spr_write;
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input spr_write;
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input [aw-1:0] spr_addr;
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input [aw-1:0] spr_addr;
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input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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output [31:0] spr_dat_o;
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output [31:0] spr_dat_o;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input scanb_rst,
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scanb_si,
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scanb_en,
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scanb_clk;
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output scanb_so;
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`endif
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//
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//
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// IC I/F
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// IC I/F
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//
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//
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input icimmu_rty_i;
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input icimmu_rty_i;
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input icimmu_err_i;
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input icimmu_err_i;
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| Line 219... |
Line 238... |
assign icpu_tag_o = icimmu_tag_i;
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assign icpu_tag_o = icimmu_tag_i;
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assign icimmu_cycstb_o = icpu_cycstb_i;
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assign icimmu_cycstb_o = icpu_cycstb_i;
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assign icpu_rty_o = icimmu_rty_i;
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assign icpu_rty_o = icimmu_rty_i;
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assign icpu_err_o = icimmu_err_i;
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assign icpu_err_o = icimmu_err_i;
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assign icimmu_ci_o = `OR1200_IMMU_CI;
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assign icimmu_ci_o = `OR1200_IMMU_CI;
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`ifdef OR1200_BIST
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assign scanb_so = scanb_si;
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`endif
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`else
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`else
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//
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//
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// ITLB SPR access
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// ITLB SPR access
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//
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//
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| Line 365... |
Line 386... |
.ppn(itlb_ppn),
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.ppn(itlb_ppn),
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.uxe(itlb_uxe),
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.uxe(itlb_uxe),
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.sxe(itlb_sxe),
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.sxe(itlb_sxe),
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.ci(itlb_ci),
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.ci(itlb_ci),
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`ifdef OR1200_BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_si),
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.scanb_so(scanb_so),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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// SPR access
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// SPR access
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.spr_cs(itlb_spr_access),
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.spr_cs(itlb_spr_access),
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.spr_write(spr_write),
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.spr_write(spr_write),
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.spr_addr(spr_addr),
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.spr_addr(spr_addr),
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.spr_dat_i(spr_dat_i),
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.spr_dat_i(spr_dat_i),
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