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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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//
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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// Fixed combinational loops.
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| Line 160... |
Line 163... |
wire itlb_en;
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wire itlb_en;
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wire itlb_ci;
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wire itlb_ci;
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wire itlb_done;
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wire itlb_done;
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wire fault;
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wire fault;
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wire miss;
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wire miss;
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wire page_cross;
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reg [31:0] icpu_adr_o;
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reg [31:0] icpu_adr_o;
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`ifdef OR1200_NO_IMMU
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`ifdef OR1200_NO_IMMU
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`else
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`else
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reg itlb_en_r;
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reg itlb_en_r;
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reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
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reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
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| Line 257... |
Line 261... |
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//
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//
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// Cut transfer if something goes wrong with translation. If IC is disabled,
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// Cut transfer if something goes wrong with translation. If IC is disabled,
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// use delayed signals.
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// use delayed signals.
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//
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//
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assign icimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i : (miss | fault) ? 1'b0 : icpu_cycstb_i;
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assign icimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross;
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//
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//
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// Cache Inhibit
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// Cache Inhibit
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//
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//
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assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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//
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//
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// Page cross
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//
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// Asserted when CPU address crosses page boundary. Most of the time it is zero.
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//
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assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icimmu_adr_o[31:`OR1200_IMMU_PS];
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//
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// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
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// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
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// one clock cycle after offset part.
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// one clock cycle after offset part.
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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