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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_immu_top.v] - Diff between revs 958 and 977

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Rev 958 Rev 977
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.8  2002/08/14 06:23:50  lampret
 
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
 
//
// Revision 1.7  2002/08/12 05:31:30  lampret
// Revision 1.7  2002/08/12 05:31:30  lampret
// Delayed external access at page crossing.
// Delayed external access at page crossing.
//
//
// Revision 1.6  2002/03/29 15:16:56  lampret
// Revision 1.6  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
// Some of the warnings fixed.
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//
//
// icpu_rty_o
// icpu_rty_o
//
//
// assign icpu_rty_o = !icpu_err_o & icimmu_rty_i;
// assign icpu_rty_o = !icpu_err_o & icimmu_rty_i;
assign icpu_rty_o = icimmu_rty_i | itlb_spr_access;
assign icpu_rty_o = icimmu_rty_i | itlb_spr_access & immu_en;
 
 
//
//
// icpu_err_o
// icpu_err_o
//
//
assign icpu_err_o = miss | fault | icimmu_err_i;
assign icpu_err_o = miss | fault | icimmu_err_i;
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//
//
// Cut transfer if something goes wrong with translation. If IC is disabled,
// Cut transfer if something goes wrong with translation. If IC is disabled,
// use delayed signals.
// use delayed signals.
//
//
assign icimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross;
// assign icimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
 
assign icimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
 
 
//
//
// Cache Inhibit
// Cache Inhibit
//
//
assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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//
//
// Physical address is either translated virtual address or
// Physical address is either translated virtual address or
// simply equal when IMMU is disabled
// simply equal when IMMU is disabled
//
//
assign icimmu_adr_o = immu_en ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]};
assign icimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
 
 
//
//
// Output to SPRS unit
// Output to SPRS unit
//
//
assign spr_dat_o = spr_cs ? itlb_dat_o : 32'h00000000;
assign spr_dat_o = spr_cs ? itlb_dat_o : 32'h00000000;

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