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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/09/08 05:52:16 lampret
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// Added optional l.div/l.divu insns. By default they are disabled.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.3 2001/10/21 17:57:16 lampret
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// Revision 1.3 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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Line 113... |
output [31:0] spr_dat_o;
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output [31:0] spr_dat_o;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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`ifdef OR1200_MULT_IMPLEMENTED
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reg [width-1:0] result;
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reg [width-1:0] result;
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reg [2*width-1:0] mul_prod_r;
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reg [2*width-1:0] mul_prod_r;
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reg [2*width-1:0] mac_r;
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`else
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wire [width-1:0] result;
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wire [2*width-1:0] mul_prod_r;
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`endif
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wire [2*width-1:0] mul_prod;
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wire [2*width-1:0] mul_prod;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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`ifdef OR1200_MAC_IMPLEMENTED
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
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reg mac_stall_r;
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reg mac_stall_r;
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reg [2*width-1:0] mac_r;
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`else
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
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wire mac_stall_r;
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wire [2*width-1:0] mac_r;
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`endif
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wire [width-1:0] x;
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wire [width-1:0] x;
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wire [width-1:0] y;
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wire [width-1:0] y;
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wire spr_maclo_we;
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wire spr_maclo_we;
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wire spr_machi_we;
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wire spr_machi_we;
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wire alu_op_div_divu;
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wire alu_op_div_divu;
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Line 150... |
`endif
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`endif
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//
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//
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// Combinatorial logic
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// Combinatorial logic
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//
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//
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`ifdef OR1200_MAC_IMPLEMENTED
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assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
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assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
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assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
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assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
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assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
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assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
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`else
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assign spr_maclo_we = 1'b0;
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assign spr_machi_we = 1'b0;
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assign spr_dat_o = 32'h0000_0000;
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`endif
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`ifdef OR1200_LOWPWR_MULT
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`ifdef OR1200_LOWPWR_MULT
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assign x = (alu_op_div & a[31]) ? ~a + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? a : 32'h0000_0000;
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assign x = (alu_op_div & a[31]) ? ~a + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? a : 32'h0000_0000;
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assign y = (alu_op_div & b[31]) ? ~b + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? b : 32'h0000_0000;
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assign y = (alu_op_div & b[31]) ? ~b + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? b : 32'h0000_0000;
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`else
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`else
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assign x = alu_op_div & a[31] ? ~a + 1'b1 : a;
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assign x = alu_op_div & a[31] ? ~a + 1'b1 : a;
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Line 175... |
`else
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`else
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assign alu_op_div = 1'b0;
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assign alu_op_div = 1'b0;
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assign alu_op_div_divu = 1'b0;
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assign alu_op_div_divu = 1'b0;
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`endif
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`endif
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`ifdef OR1200_MULT_IMPLEMENTED
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//
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//
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// Select result of current ALU operation to be forwarded
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// Select result of current ALU operation to be forwarded
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// to next instruction and to WB stage
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// to next instruction and to WB stage
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//
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//
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always @(alu_op or mul_prod_r or mac_r or a or b)
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always @(alu_op or mul_prod_r or mac_r or a or b)
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Line 206... |
.Y(y),
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.Y(y),
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.RST(rst),
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.RST(rst),
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.CLK(clk),
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.CLK(clk),
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.P(mul_prod)
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.P(mul_prod)
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);
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);
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`else
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`else // OR1200_ASIC_MULTP2_32X32
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or1200_gmultp2_32x32 or1200_gmultp2_32x32(
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or1200_gmultp2_32x32 or1200_gmultp2_32x32(
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.X(x),
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.X(x),
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.Y(y),
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.Y(y),
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.RST(rst),
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.RST(rst),
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.CLK(clk),
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.CLK(clk),
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.P(mul_prod)
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.P(mul_prod)
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);
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);
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`endif
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`endif // OR1200_ASIC_MULTP2_32X32
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//
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//
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// Registered output from the multiplier and
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// Registered output from the multiplier and
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// an optional divider
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// an optional divider
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//
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//
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Line 241... |
else if (alu_op_div_divu && div_free) begin
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else if (alu_op_div_divu && div_free) begin
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mul_prod_r <= #1 {31'b0, x[31:0], 1'b0};
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mul_prod_r <= #1 {31'b0, x[31:0], 1'b0};
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div_cntr <= #1 6'b10_0000;
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div_cntr <= #1 6'b10_0000;
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div_free <= #1 1'b0;
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div_free <= #1 1'b0;
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end
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end
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`endif
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`endif // OR1200_IMPL_DIV
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else if (div_free | !ex_freeze) begin
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else if (div_free | !ex_freeze) begin
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mul_prod_r <= #1 mul_prod[63:0];
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mul_prod_r <= #1 mul_prod[63:0];
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div_free <= #1 1'b1;
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div_free <= #1 1'b1;
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end
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end
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`else // OR1200_MULT_IMPLEMENTED
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assign result = {width{1'b0}};
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assign mul_prod = {2*width{1'b0}};
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assign mul_prod_r = {2*width{1'b0}};
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`endif // OR1200_MULT_IMPLEMENTED
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`ifdef OR1200_MAC_IMPLEMENTED
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//
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//
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// Propagation of l.mac opcode
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// Propagation of l.mac opcode
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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Line 315... |
mac_stall_r <= #1 (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & id_macrc_op
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mac_stall_r <= #1 (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & id_macrc_op
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`ifdef OR1200_IMPL_DIV
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`ifdef OR1200_IMPL_DIV
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| (|div_cntr)
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| (|div_cntr)
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`endif
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`endif
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;
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;
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`else // OR1200_MAC_IMPLEMENTED
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assign mac_stall_r = 1'b0;
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assign mac_r = {2*width{1'b0}};
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assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
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assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
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assign mac_op_r3 = `OR1200_MACOP_WIDTH'b0;
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`endif // OR1200_MAC_IMPLEMENTED
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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