| Line 45... |
Line 45... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1.2.3 2003/12/17 13:36:58 simons
|
|
// Qmem mbist signals fixed.
|
|
//
|
// Revision 1.1.2.2 2003/12/09 11:46:48 simons
|
// Revision 1.1.2.2 2003/12/09 11:46:48 simons
|
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
|
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
|
//
|
//
|
// Revision 1.1.2.1 2003/07/08 15:45:26 lampret
|
// Revision 1.1.2.1 2003/07/08 15:45:26 lampret
|
// Added embedded memory QMEM.
|
// Added embedded memory QMEM.
|
| Line 215... |
Line 218... |
reg qmem_iack;
|
reg qmem_iack;
|
wire [31:0] qmem_di;
|
wire [31:0] qmem_di;
|
wire [31:0] qmem_do;
|
wire [31:0] qmem_do;
|
wire qmem_en;
|
wire qmem_en;
|
wire qmem_we;
|
wire qmem_we;
|
|
`ifdef OR1200_QMEM_BSEL
|
|
wire [3:0] qmem_sel;
|
|
`endif
|
wire [31:0] qmem_addr;
|
wire [31:0] qmem_addr;
|
|
`ifdef OR1200_QMEM_ACK
|
|
wire qmem_ack;
|
|
`else
|
|
wire qmem_ack = 1'b1;
|
|
`endif
|
|
|
//
|
//
|
// QMEM and CPU/IMMU
|
// QMEM and CPU/IMMU
|
//
|
//
|
assign qmemicpu_dat_o = qmem_iack ? qmem_do : icqmem_dat_i;
|
assign qmemicpu_dat_o = qmem_iack ? qmem_do : icqmem_dat_i;
|
| Line 240... |
Line 251... |
//
|
//
|
// QMEM and CPU/DMMU
|
// QMEM and CPU/DMMU
|
//
|
//
|
assign qmemdcpu_dat_o = daddr_qmem_hit ? qmem_do : dcqmem_dat_i;
|
assign qmemdcpu_dat_o = daddr_qmem_hit ? qmem_do : dcqmem_dat_i;
|
assign qmemdcpu_ack_o = daddr_qmem_hit ? qmem_dack : dcqmem_ack_i;
|
assign qmemdcpu_ack_o = daddr_qmem_hit ? qmem_dack : dcqmem_ack_i;
|
assign qmemdcpu_rty_o = daddr_qmem_hit ? 1'b0 : dcqmem_rty_i;
|
assign qmemdcpu_rty_o = daddr_qmem_hit ? ~qmem_dack : dcqmem_rty_i;
|
assign qmemdmmu_err_o = daddr_qmem_hit ? 1'b0 : dcqmem_err_i;
|
assign qmemdmmu_err_o = daddr_qmem_hit ? 1'b0 : dcqmem_err_i;
|
assign qmemdmmu_tag_o = daddr_qmem_hit ? 4'h0 : dcqmem_tag_i;
|
assign qmemdmmu_tag_o = daddr_qmem_hit ? 4'h0 : dcqmem_tag_i;
|
|
|
//
|
//
|
// QMEM and DC
|
// QMEM and DC
|
| Line 258... |
Line 269... |
assign dcqmem_dat_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdcpu_dat_i;
|
assign dcqmem_dat_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdcpu_dat_i;
|
|
|
//
|
//
|
// Address comparison whether QMEM was hit
|
// Address comparison whether QMEM was hit
|
//
|
//
|
assign iaddr_qmem_hit = (qmemimmu_adr_i & `OR1200_QMEM_MASK) == `OR1200_QMEM_ADDR;
|
`ifdef OR1200_QMEM_IADDR
|
assign daddr_qmem_hit = (qmemdmmu_adr_i & `OR1200_QMEM_MASK) == `OR1200_QMEM_ADDR;
|
assign iaddr_qmem_hit = (qmemimmu_adr_i & `OR1200_QMEM_IMASK) == `OR1200_QMEM_IADDR;
|
|
`else
|
|
assign iaddr_qmem_hit = 1'b0;
|
|
`endif
|
|
|
|
`ifdef OR1200_QMEM_DADDR
|
|
assign daddr_qmem_hit = (qmemdmmu_adr_i & `OR1200_QMEM_DMASK) == `OR1200_QMEM_DADDR;
|
|
`else
|
|
assign daddr_qmem_hit = 1'b0;
|
|
`endif
|
|
|
//
|
//
|
//
|
//
|
//
|
//
|
assign qmem_en = iaddr_qmem_hit & qmemimmu_cycstb_i | daddr_qmem_hit & qmemdmmu_cycstb_i;
|
assign qmem_en = iaddr_qmem_hit & qmemimmu_cycstb_i | daddr_qmem_hit & qmemdmmu_cycstb_i;
|
assign qmem_we = qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i;
|
assign qmem_we = qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i;
|
|
`ifdef OR1200_QMEM_BSEL
|
|
assign qmem_sel = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdcpu_sel_i : qmemicpu_sel_i;
|
|
`endif
|
assign qmem_di = qmemdcpu_dat_i;
|
assign qmem_di = qmemdcpu_dat_i;
|
assign qmem_addr = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdmmu_adr_i : qmemimmu_adr_i;
|
assign qmem_addr = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdmmu_adr_i : qmemimmu_adr_i;
|
|
|
//
|
//
|
// QMEM control FSM
|
// QMEM control FSM
|
| Line 280... |
Line 303... |
qmem_dack <= #1 1'b0;
|
qmem_dack <= #1 1'b0;
|
qmem_iack <= #1 1'b0;
|
qmem_iack <= #1 1'b0;
|
end
|
end
|
else case (state) // synopsys parallel_case
|
else case (state) // synopsys parallel_case
|
`OR1200_QMEMFSM_IDLE: begin
|
`OR1200_QMEMFSM_IDLE: begin
|
if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin
|
if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
|
state <= #1 `OR1200_QMEMFSM_STORE;
|
state <= #1 `OR1200_QMEMFSM_STORE;
|
qmem_dack <= #1 1'b1;
|
qmem_dack <= #1 1'b1;
|
qmem_iack <= #1 1'b0;
|
qmem_iack <= #1 1'b0;
|
end
|
end
|
else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin
|
else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
|
state <= #1 `OR1200_QMEMFSM_LOAD;
|
state <= #1 `OR1200_QMEMFSM_LOAD;
|
qmem_dack <= #1 1'b1;
|
qmem_dack <= #1 1'b1;
|
qmem_iack <= #1 1'b0;
|
qmem_iack <= #1 1'b0;
|
end
|
end
|
else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin
|
else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
|
state <= #1 `OR1200_QMEMFSM_FETCH;
|
state <= #1 `OR1200_QMEMFSM_FETCH;
|
qmem_iack <= #1 1'b1;
|
qmem_iack <= #1 1'b1;
|
qmem_dack <= #1 1'b0;
|
qmem_dack <= #1 1'b0;
|
end
|
end
|
end
|
end
|
`OR1200_QMEMFSM_STORE: begin
|
`OR1200_QMEMFSM_STORE: begin
|
if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin
|
if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
|
state <= #1 `OR1200_QMEMFSM_STORE;
|
state <= #1 `OR1200_QMEMFSM_STORE;
|
qmem_dack <= #1 1'b1;
|
qmem_dack <= #1 1'b1;
|
qmem_iack <= #1 1'b0;
|
qmem_iack <= #1 1'b0;
|
end
|
end
|
else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin
|
else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
|
state <= #1 `OR1200_QMEMFSM_LOAD;
|
state <= #1 `OR1200_QMEMFSM_LOAD;
|
qmem_dack <= #1 1'b1;
|
qmem_dack <= #1 1'b1;
|
qmem_iack <= #1 1'b0;
|
qmem_iack <= #1 1'b0;
|
end
|
end
|
else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin
|
else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
|
state <= #1 `OR1200_QMEMFSM_FETCH;
|
state <= #1 `OR1200_QMEMFSM_FETCH;
|
qmem_iack <= #1 1'b1;
|
qmem_iack <= #1 1'b1;
|
qmem_dack <= #1 1'b0;
|
qmem_dack <= #1 1'b0;
|
end
|
end
|
else begin
|
else begin
|
| Line 319... |
Line 342... |
qmem_dack <= #1 1'b0;
|
qmem_dack <= #1 1'b0;
|
qmem_iack <= #1 1'b0;
|
qmem_iack <= #1 1'b0;
|
end
|
end
|
end
|
end
|
`OR1200_QMEMFSM_LOAD: begin
|
`OR1200_QMEMFSM_LOAD: begin
|
if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin
|
if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
|
state <= #1 `OR1200_QMEMFSM_STORE;
|
state <= #1 `OR1200_QMEMFSM_STORE;
|
qmem_dack <= #1 1'b1;
|
qmem_dack <= #1 1'b1;
|
qmem_iack <= #1 1'b0;
|
qmem_iack <= #1 1'b0;
|
end
|
end
|
else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin
|
else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
|
state <= #1 `OR1200_QMEMFSM_LOAD;
|
state <= #1 `OR1200_QMEMFSM_LOAD;
|
qmem_dack <= #1 1'b1;
|
qmem_dack <= #1 1'b1;
|
qmem_iack <= #1 1'b0;
|
qmem_iack <= #1 1'b0;
|
end
|
end
|
else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin
|
else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
|
state <= #1 `OR1200_QMEMFSM_FETCH;
|
state <= #1 `OR1200_QMEMFSM_FETCH;
|
qmem_iack <= #1 1'b1;
|
qmem_iack <= #1 1'b1;
|
qmem_dack <= #1 1'b0;
|
qmem_dack <= #1 1'b0;
|
end
|
end
|
else begin
|
else begin
|
| Line 341... |
Line 364... |
qmem_dack <= #1 1'b0;
|
qmem_dack <= #1 1'b0;
|
qmem_iack <= #1 1'b0;
|
qmem_iack <= #1 1'b0;
|
end
|
end
|
end
|
end
|
`OR1200_QMEMFSM_FETCH: begin
|
`OR1200_QMEMFSM_FETCH: begin
|
if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin
|
if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
|
state <= #1 `OR1200_QMEMFSM_STORE;
|
state <= #1 `OR1200_QMEMFSM_STORE;
|
qmem_dack <= #1 1'b1;
|
qmem_dack <= #1 1'b1;
|
qmem_iack <= #1 1'b0;
|
qmem_iack <= #1 1'b0;
|
end
|
end
|
else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin
|
else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
|
state <= #1 `OR1200_QMEMFSM_LOAD;
|
state <= #1 `OR1200_QMEMFSM_LOAD;
|
qmem_dack <= #1 1'b1;
|
qmem_dack <= #1 1'b1;
|
qmem_iack <= #1 1'b0;
|
qmem_iack <= #1 1'b0;
|
end
|
end
|
else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin
|
else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
|
state <= #1 `OR1200_QMEMFSM_FETCH;
|
state <= #1 `OR1200_QMEMFSM_FETCH;
|
qmem_iack <= #1 1'b1;
|
qmem_iack <= #1 1'b1;
|
qmem_dack <= #1 1'b0;
|
qmem_dack <= #1 1'b0;
|
end
|
end
|
else begin
|
else begin
|
| Line 377... |
Line 400... |
.mbist_si_i(mbist_si_i),
|
.mbist_si_i(mbist_si_i),
|
.mbist_so_o(mbist_so_o),
|
.mbist_so_o(mbist_so_o),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
`endif
|
`endif
|
.addr(qmem_addr[12:2]),
|
.addr(qmem_addr[12:2]),
|
|
`ifdef OR1200_QMEM_BSEL
|
|
.sel(qmem_sel),
|
|
`endif
|
|
`ifdef OR1200_QMEM_ACK
|
|
.ack(qmem_ack),
|
|
`endif
|
.ce(qmem_en),
|
.ce(qmem_en),
|
.we(qmem_we),
|
.we(qmem_we),
|
.oe(1'b1),
|
.oe(1'b1),
|
.di(qmem_di),
|
.di(qmem_di),
|
.do(qmem_do)
|
.do(qmem_do)
|
