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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2003/04/07 01:19:07 lampret
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// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
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//
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// Revision 1.2 2002/10/17 20:04:40 lampret
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// Revision 1.2 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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defparam lpm_ram_dq_component.lpm_width = dw,
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defparam lpm_ram_dq_component.lpm_width = dw,
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lpm_ram_dq_component.lpm_widthad = aw,
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lpm_ram_dq_component.lpm_widthad = aw,
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lpm_ram_dq_component.lpm_indata = "REGISTERED",
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lpm_ram_dq_component.lpm_indata = "REGISTERED",
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lpm_ram_dq_component.lpm_address_control = "REGISTERED",
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lpm_ram_dq_component.lpm_address_control = "REGISTERED",
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lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
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lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
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lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
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lpm_ram_dq_component.lpm_hint = "USE_EAB=OFF";
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// examplar attribute lpm_ram_dq_component NOOPT TRUE
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// examplar attribute lpm_ram_dq_component NOOPT TRUE
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`else
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`else
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//
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//
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