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https://opencores.org/ocsvn/or1k/or1k/trunk
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.4 2002/01/23 07:52:36 lampret
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// Revision 1.4 2002/01/23 07:52:36 lampret
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// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
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// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
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//
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//
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// Revision 1.3 2002/01/19 09:27:49 lampret
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// Revision 1.3 2002/01/19 09:27:49 lampret
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// SR[TEE] should be zero after reset.
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// SR[TEE] should be zero after reset.
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//
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//
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// Generate SPR address from base address and offset
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// Generate SPR address from base address and offset
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// OR from debug unit address
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// OR from debug unit address
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//
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//
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assign spr_addr = du_access ? du_addr : addrbase + {16'h0000, addrofs};
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assign spr_addr = du_access ? du_addr : addrbase | {16'h0000, addrofs};
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//
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//
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// SPR is written by debug unit or by l.mtspr
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// SPR is written by debug unit or by l.mtspr
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//
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//
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assign spr_dat_o = du_write ? du_dat_du : dat_i;
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assign spr_dat_o = du_write ? du_dat_du : dat_i;
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