URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Diff between revs 504 and 589

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Rev 504	Rev 589
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2002/01/03 08:16:15 lampret`
	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
	`//`
`// Revision 1.13 2001/11/23 08:38:51 lampret`	`// Revision 1.13 2001/11/23 08:38:51 lampret`
`// Changed DSR/DRR behavior and exception detection.`	`// Changed DSR/DRR behavior and exception detection.`
`//`	`//`
`// Revision 1.12 2001/11/20 00:57:22 lampret`	`// Revision 1.12 2001/11/20 00:57:22 lampret`
`// Fixed width of du_except.`	`// Fixed width of du_except.`
Line 293...	Line 296...
`//`	`//`
`// Connection between CPU and PIC`	`// Connection between CPU and PIC`
`//`	`//`
`wire [dw-1:0] spr_dat_pic;`	`wire [dw-1:0] spr_dat_pic;`
`wire pic_wakeup;`	`wire pic_wakeup;`
`wire int_low;`	`wire sig_int;`
`wire int_high;`
`wire int_high_tt;`

`//`	`//`
`// Connection between CPU and PM`	`// Connection between CPU and PM`
`//`	`//`
`wire [dw-1:0] spr_dat_pm;`	`wire [dw-1:0] spr_dat_pm;`

`//`	`//`
`// CPU and TT`	`// CPU and TT`
`//`	`//`
`wire [dw-1:0] spr_dat_tt;`	`wire [dw-1:0] spr_dat_tt;`
`wire tt_int;`	`wire sig_tick;`

`//`	`//`
`// Debug port and caches/MMUs`	`// Debug port and caches/MMUs`
`//`	`//`
`wire [dw-1:0] spr_dat_du;`	`wire [dw-1:0] spr_dat_du;`
Line 326...	Line 327...
`wire ex_freeze;`	`wire ex_freeze;`
`wire [31:0] ex_insn;`	`wire [31:0] ex_insn;`
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;	wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;

`//`	`//`
`// Assignments`
`//`
`assign int_high_tt = int_high \| tt_int;`

`//`
`// Instantiation of Instruction WISHBONE BIU`	`// Instantiation of Instruction WISHBONE BIU`
`//`	`//`
`or1200_wb_biu iwb_biu(`	`or1200_wb_biu iwb_biu(`
`// RISC clk, rst and clock control`	`// RISC clk, rst and clock control`
`.clk(clk_i),`	`.clk(clk_i),`
Line 535...	Line 531...

`// Connection DMMU and CPU internally`	`// Connection DMMU and CPU internally`
`.dmmu_en(dmmu_en),`	`.dmmu_en(dmmu_en),`

`// Connection PIC and CPU's EXCEPT`	`// Connection PIC and CPU's EXCEPT`
`.int_high(int_high_tt),`	`.sig_int(sig_int),`
`.int_low(int_low),`	`.sig_tick(sig_tick),`

`// SPRs`	`// SPRs`
`.supv(supv),`	`.supv(supv),`
`.spr_addr(spr_addr),`	`.spr_addr(spr_addr),`
`.spr_dataout(spr_dat_cpu),`	`.spr_dataout(spr_dat_cpu),`
Line 687...	Line 683...
`.spr_write(spr_we),`	`.spr_write(spr_we),`
`.spr_addr(spr_addr),`	`.spr_addr(spr_addr),`
`.spr_dat_i(spr_dat_cpu),`	`.spr_dat_i(spr_dat_cpu),`
`.spr_dat_o(spr_dat_pic),`	`.spr_dat_o(spr_dat_pic),`
`.pic_wakeup(pic_wakeup),`	`.pic_wakeup(pic_wakeup),`
`.int_low(int_low),`	`.int(sig_int),`
`.int_high(int_high),`

`// PIC Interface`	`// PIC Interface`
`.pic_int(pic_ints_i)`	`.pic_int(pic_ints_i)`
`);`	`);`

Line 706...	Line 701...
.spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]),	.spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]),
`.spr_write(spr_we),`	`.spr_write(spr_we),`
`.spr_addr(spr_addr),`	`.spr_addr(spr_addr),`
`.spr_dat_i(spr_dat_cpu),`	`.spr_dat_i(spr_dat_cpu),`
`.spr_dat_o(spr_dat_tt),`	`.spr_dat_o(spr_dat_tt),`
`.int(tt_int)`	`.int(sig_tick)`
`);`	`);`

`//`	`//`
`// Instantiation of Power Management`	`// Instantiation of Power Management`
`//`	`//`

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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Diff between revs 504 and 589