| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/02/01 19:56:55 lampret
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// Fixed combinational loops.
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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| Line 245... |
Line 248... |
// DMMU and DC
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// DMMU and DC
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//
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//
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wire dcdmmu_err_dc;
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wire dcdmmu_err_dc;
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wire [3:0] dcdmmu_tag_dc;
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wire [3:0] dcdmmu_tag_dc;
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wire [aw-1:0] dcdmmu_adr_dmmu;
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wire [aw-1:0] dcdmmu_adr_dmmu;
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wire dcdmmu_cyc_dmmu;
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wire dcdmmu_cycstb_dmmu;
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wire dcdmmu_stb_dmmu;
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wire dcdmmu_ci_dmmu;
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wire dcdmmu_ci_dmmu;
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//
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//
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// CPU and data memory subsystem
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// CPU and data memory subsystem
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//
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//
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| Line 275... |
Line 277... |
//
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//
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// CPU and insn memory subsystem
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// CPU and insn memory subsystem
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//
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//
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wire ic_en;
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wire ic_en;
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wire [31:0] icpu_adr_cpu;
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wire [31:0] icpu_adr_cpu;
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wire icpu_cyc_cpu;
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wire icpu_cycstb_cpu;
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wire icpu_stb_cpu;
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wire icpu_we_cpu;
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wire icpu_we_cpu;
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wire [3:0] icpu_sel_cpu;
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wire [3:0] icpu_sel_cpu;
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wire [3:0] icpu_tag_cpu;
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wire [3:0] icpu_tag_cpu;
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wire [31:0] icpu_dat_ic;
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wire [31:0] icpu_dat_ic;
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wire icpu_ack_ic;
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wire icpu_ack_ic;
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| Line 293... |
Line 294... |
//
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//
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wire [aw-1:0] icimmu_adr_immu;
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wire [aw-1:0] icimmu_adr_immu;
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wire icimmu_rty_ic;
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wire icimmu_rty_ic;
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wire icimmu_err_ic;
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wire icimmu_err_ic;
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wire [3:0] icimmu_tag_ic;
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wire [3:0] icimmu_tag_ic;
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wire icimmu_cyc_immu;
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wire icimmu_cycstb_immu;
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wire icimmu_stb_immu;
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wire icimmu_ci_immu;
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wire icimmu_ci_immu;
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//
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//
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// Connection between CPU and PIC
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// Connection between CPU and PIC
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//
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//
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| Line 419... |
Line 419... |
// CPU i/f
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// CPU i/f
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.ic_en(ic_en),
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.ic_en(ic_en),
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.immu_en(immu_en),
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.immu_en(immu_en),
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.supv(supv),
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.supv(supv),
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.icpu_adr_i(icpu_adr_cpu),
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.icpu_adr_i(icpu_adr_cpu),
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.icpu_cyc_i(icpu_cyc_cpu),
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.icpu_cycstb_i(icpu_cycstb_cpu),
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.icpu_stb_i(icpu_stb_cpu),
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.icpu_adr_o(icpu_adr_immu),
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.icpu_adr_o(icpu_adr_immu),
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.icpu_tag_o(icpu_tag_immu),
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.icpu_tag_o(icpu_tag_immu),
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.icpu_rty_o(icpu_rty_immu),
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.icpu_rty_o(icpu_rty_immu),
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.icpu_err_o(icpu_err_immu),
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.icpu_err_o(icpu_err_immu),
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| Line 438... |
Line 437... |
// IC i/f
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// IC i/f
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.icimmu_rty_i(icimmu_rty_ic),
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.icimmu_rty_i(icimmu_rty_ic),
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.icimmu_err_i(icimmu_err_ic),
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.icimmu_err_i(icimmu_err_ic),
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.icimmu_tag_i(icimmu_tag_ic),
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.icimmu_tag_i(icimmu_tag_ic),
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.icimmu_adr_o(icimmu_adr_immu),
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.icimmu_adr_o(icimmu_adr_immu),
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.icimmu_cyc_o(icimmu_cyc_immu),
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.icimmu_cycstb_o(icimmu_cycstb_immu),
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.icimmu_stb_o(icimmu_stb_immu),
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.icimmu_ci_o(icimmu_ci_immu)
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.icimmu_ci_o(icimmu_ci_immu)
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);
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);
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//
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//
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// Instantiation of Instruction Cache
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// Instantiation of Instruction Cache
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| Line 453... |
Line 451... |
.rst(rst_i),
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.rst(rst_i),
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// IC and CPU/IMMU
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// IC and CPU/IMMU
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.ic_en(ic_en),
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.ic_en(ic_en),
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.icimmu_adr_i(icimmu_adr_immu),
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.icimmu_adr_i(icimmu_adr_immu),
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.icimmu_cyc_i(icimmu_cyc_immu),
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.icimmu_cycstb_i(icimmu_cycstb_immu),
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.icimmu_stb_i(icimmu_stb_immu),
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.icimmu_ci_i(icimmu_ci_immu),
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.icimmu_ci_i(icimmu_ci_immu),
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.icpu_we_i(icpu_we_cpu),
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.icpu_we_i(icpu_we_cpu),
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.icpu_sel_i(icpu_sel_cpu),
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.icpu_sel_i(icpu_sel_cpu),
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.icpu_tag_i(icpu_tag_cpu),
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.icpu_tag_i(icpu_tag_cpu),
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.icpu_dat_o(icpu_dat_ic),
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.icpu_dat_o(icpu_dat_ic),
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| Line 493... |
Line 490... |
.rst(rst_i),
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.rst(rst_i),
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// Connection IC and IFETCHER inside CPU
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// Connection IC and IFETCHER inside CPU
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.ic_en(ic_en),
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.ic_en(ic_en),
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.icpu_adr_o(icpu_adr_cpu),
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.icpu_adr_o(icpu_adr_cpu),
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.icpu_cyc_o(icpu_cyc_cpu),
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.icpu_cycstb_o(icpu_cycstb_cpu),
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.icpu_stb_o(icpu_stb_cpu),
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.icpu_we_o(icpu_we_cpu),
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.icpu_we_o(icpu_we_cpu),
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.icpu_sel_o(icpu_sel_cpu),
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.icpu_sel_o(icpu_sel_cpu),
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.icpu_tag_o(icpu_tag_cpu),
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.icpu_tag_o(icpu_tag_cpu),
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.icpu_dat_i(icpu_dat_ic),
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.icpu_dat_i(icpu_dat_ic),
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.icpu_ack_i(icpu_ack_ic),
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.icpu_ack_i(icpu_ack_ic),
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| Line 524... |
Line 520... |
.immu_en(immu_en),
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.immu_en(immu_en),
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// Connection DC and CPU
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// Connection DC and CPU
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.dc_en(dc_en),
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.dc_en(dc_en),
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.dcpu_adr_o(dcpu_adr_cpu),
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.dcpu_adr_o(dcpu_adr_cpu),
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.dcpu_cyc_o(dcpu_cyc_cpu),
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.dcpu_cycstb_o(dcpu_cycstb_cpu),
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.dcpu_stb_o(dcpu_stb_cpu),
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.dcpu_we_o(dcpu_we_cpu),
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.dcpu_we_o(dcpu_we_cpu),
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.dcpu_sel_o(dcpu_sel_cpu),
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.dcpu_sel_o(dcpu_sel_cpu),
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.dcpu_tag_o(dcpu_tag_cpu),
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.dcpu_tag_o(dcpu_tag_cpu),
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.dcpu_dat_o(dcpu_dat_cpu),
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.dcpu_dat_o(dcpu_dat_cpu),
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.dcpu_dat_i(dcpu_dat_dc),
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.dcpu_dat_i(dcpu_dat_dc),
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| Line 570... |
Line 565... |
// CPU i/f
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// CPU i/f
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.dc_en(dc_en),
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.dc_en(dc_en),
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.dmmu_en(dmmu_en),
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.dmmu_en(dmmu_en),
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.supv(supv),
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.supv(supv),
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.dcpu_adr_i(dcpu_adr_cpu),
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.dcpu_adr_i(dcpu_adr_cpu),
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.dcpu_cyc_i(dcpu_cyc_cpu),
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.dcpu_cycstb_i(dcpu_cycstb_cpu),
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.dcpu_stb_i(dcpu_stb_cpu),
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.dcpu_we_i(dcpu_we_cpu),
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.dcpu_we_i(dcpu_we_cpu),
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.dcpu_tag_o(dcpu_tag_dmmu),
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.dcpu_tag_o(dcpu_tag_dmmu),
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.dcpu_err_o(dcpu_err_dmmu),
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.dcpu_err_o(dcpu_err_dmmu),
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|
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// SPR access
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// SPR access
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| Line 587... |
Line 581... |
|
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// DC i/f
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// DC i/f
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.dcdmmu_err_i(dcdmmu_err_dc),
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.dcdmmu_err_i(dcdmmu_err_dc),
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.dcdmmu_tag_i(dcdmmu_tag_dc),
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.dcdmmu_tag_i(dcdmmu_tag_dc),
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.dcdmmu_adr_o(dcdmmu_adr_dmmu),
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.dcdmmu_adr_o(dcdmmu_adr_dmmu),
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.dcdmmu_cyc_o(dcdmmu_cyc_dmmu),
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.dcdmmu_cycstb_o(dcdmmu_cycstb_dmmu),
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.dcdmmu_stb_o(dcdmmu_stb_dmmu),
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.dcdmmu_ci_o(dcdmmu_ci_dmmu)
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.dcdmmu_ci_o(dcdmmu_ci_dmmu)
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);
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);
|
|
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//
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//
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// Instantiation of Data Cache
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// Instantiation of Data Cache
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| Line 602... |
Line 595... |
.rst(rst_i),
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.rst(rst_i),
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|
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// DC and CPU/DMMU
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// DC and CPU/DMMU
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.dc_en(dc_en),
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.dc_en(dc_en),
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.dcdmmu_adr_i(dcdmmu_adr_dmmu),
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.dcdmmu_adr_i(dcdmmu_adr_dmmu),
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.dcdmmu_cyc_i(dcdmmu_cyc_dmmu),
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.dcdmmu_cycstb_i(dcdmmu_cycstb_dmmu),
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.dcdmmu_stb_i(dcdmmu_stb_dmmu),
|
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.dcdmmu_ci_i(dcdmmu_ci_dmmu),
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.dcdmmu_ci_i(dcdmmu_ci_dmmu),
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.dcpu_we_i(dcpu_we_cpu),
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.dcpu_we_i(dcpu_we_cpu),
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.dcpu_sel_i(dcpu_sel_cpu),
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.dcpu_sel_i(dcpu_sel_cpu),
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.dcpu_tag_i(dcpu_tag_cpu),
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.dcpu_tag_i(dcpu_tag_cpu),
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.dcpu_dat_i(dcpu_dat_cpu),
|
.dcpu_dat_i(dcpu_dat_cpu),
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| Line 640... |
Line 632... |
//
|
//
|
or1200_du or1200_du(
|
or1200_du or1200_du(
|
// RISC Internal Interface
|
// RISC Internal Interface
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
.dcpu_cyc_i(dcpu_cyc_cpu),
|
.dcpu_cycstb_i(dcpu_cycstb_cpu),
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.dcpu_stb_i(dcpu_stb_cpu),
|
|
.dcpu_we_i(dcpu_we_cpu),
|
.dcpu_we_i(dcpu_we_cpu),
|
.icpu_cyc_i(icpu_cyc_cpu),
|
.icpu_cycstb_i(icpu_cycstb_cpu),
|
.icpu_stb_i(icpu_stb_cpu),
|
|
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.branch_op(branch_op),
|
.branch_op(branch_op),
|
.ex_insn(ex_insn),
|
.ex_insn(ex_insn),
|
.du_dsr(du_dsr),
|
.du_dsr(du_dsr),
|
|
|
