| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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// Revision 1.6 2002/03/29 15:16:56 lampret
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// Revision 1.6 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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//
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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| Line 204... |
Line 207... |
//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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//
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//
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// DC to BIU
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// DC to SB
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//
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//
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wire [dw-1:0] dcbiu_dat_dc;
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wire [dw-1:0] dcsb_dat_dc;
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wire [aw-1:0] dcbiu_adr_dc;
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wire [aw-1:0] dcsb_adr_dc;
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wire dcbiu_cyc_dc;
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wire dcsb_cyc_dc;
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wire dcbiu_stb_dc;
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wire dcsb_stb_dc;
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wire dcbiu_we_dc;
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wire dcsb_we_dc;
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wire [3:0] dcbiu_sel_dc;
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wire [3:0] dcsb_sel_dc;
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wire [3:0] dcbiu_tag_dc;
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wire dcsb_cab_dc;
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wire [dw-1:0] dcbiu_dat_biu;
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wire [dw-1:0] dcsb_dat_sb;
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wire dcbiu_ack_biu;
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wire dcsb_ack_sb;
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wire dcbiu_err_biu;
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wire dcsb_err_sb;
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wire [3:0] dcbiu_tag_biu;
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//
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// SB to BIU
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//
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wire [dw-1:0] sbbiu_dat_sb;
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wire [aw-1:0] sbbiu_adr_sb;
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wire sbbiu_cyc_sb;
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wire sbbiu_stb_sb;
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wire sbbiu_we_sb;
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wire [3:0] sbbiu_sel_sb;
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wire sbbiu_cab_sb;
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wire [dw-1:0] sbbiu_dat_biu;
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wire sbbiu_ack_biu;
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wire sbbiu_err_biu;
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//
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//
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// IC to BIU
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// IC to BIU
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//
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//
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wire [dw-1:0] icbiu_dat_ic;
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wire [dw-1:0] icbiu_dat_ic;
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| Line 402... |
Line 418... |
.wb_sel_o(dwb_sel_o),
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.wb_sel_o(dwb_sel_o),
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.wb_cab_o(dwb_cab_o),
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.wb_cab_o(dwb_cab_o),
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.wb_dat_o(dwb_dat_o),
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.wb_dat_o(dwb_dat_o),
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// Internal RISC bus
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// Internal RISC bus
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.biu_dat_i(dcbiu_dat_dc),
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.biu_dat_i(sbbiu_dat_sb),
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.biu_adr_i(dcbiu_adr_dc),
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.biu_adr_i(sbbiu_adr_sb),
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.biu_cyc_i(dcbiu_cyc_dc),
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.biu_cyc_i(sbbiu_cyc_sb),
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.biu_stb_i(dcbiu_stb_dc),
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.biu_stb_i(sbbiu_stb_sb),
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.biu_we_i(dcbiu_we_dc),
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.biu_we_i(sbbiu_we_sb),
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.biu_sel_i(dcbiu_sel_dc),
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.biu_sel_i(sbbiu_sel_sb),
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.biu_cab_i(dcbiu_cab_dc),
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.biu_cab_i(sbbiu_cab_sb),
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.biu_dat_o(dcbiu_dat_biu),
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.biu_dat_o(sbbiu_dat_biu),
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.biu_ack_o(dcbiu_ack_biu),
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.biu_ack_o(sbbiu_ack_biu),
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.biu_err_o(dcbiu_err_biu)
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.biu_err_o(sbbiu_err_biu)
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);
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);
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//
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//
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// Instantiation of IMMU
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// Instantiation of IMMU
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//
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//
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| Line 622... |
Line 638... |
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
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.spr_write(spr_we),
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.spr_write(spr_we),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_i(spr_dat_cpu),
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// DC and BIU
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// DC and BIU
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.dcbiu_dat_o(dcbiu_dat_dc),
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.dcsb_dat_o(dcsb_dat_dc),
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.dcbiu_adr_o(dcbiu_adr_dc),
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.dcsb_adr_o(dcsb_adr_dc),
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.dcbiu_cyc_o(dcbiu_cyc_dc),
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.dcsb_cyc_o(dcsb_cyc_dc),
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.dcbiu_stb_o(dcbiu_stb_dc),
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.dcsb_stb_o(dcsb_stb_dc),
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.dcbiu_we_o(dcbiu_we_dc),
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.dcsb_we_o(dcsb_we_dc),
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.dcbiu_sel_o(dcbiu_sel_dc),
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.dcsb_sel_o(dcsb_sel_dc),
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.dcbiu_cab_o(dcbiu_cab_dc),
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.dcsb_cab_o(dcsb_cab_dc),
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.dcbiu_dat_i(dcbiu_dat_biu),
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.dcsb_dat_i(dcsb_dat_sb),
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.dcbiu_ack_i(dcbiu_ack_biu),
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.dcsb_ack_i(dcsb_ack_sb),
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.dcbiu_err_i(dcbiu_err_biu)
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.dcsb_err_i(dcsb_err_sb)
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);
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//
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// Instantiation of Store Buffer
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//
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or1200_sb or1200_sb(
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// RISC clock, reset
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.clk(clk_i),
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.rst(rst_i),
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// Internal RISC bus (DC<->SB)
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.dcsb_dat_i(dcsb_dat_dc),
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.dcsb_adr_i(dcsb_adr_dc),
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.dcsb_cyc_i(dcsb_cyc_dc),
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.dcsb_stb_i(dcsb_stb_dc),
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.dcsb_we_i(dcsb_we_dc),
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.dcsb_sel_i(dcsb_sel_dc),
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.dcsb_cab_i(dcsb_cab_dc),
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.dcsb_dat_o(dcsb_dat_sb),
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.dcsb_ack_o(dcsb_ack_sb),
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.dcsb_err_o(dcsb_err_sb),
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// SB and BIU
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.sbbiu_dat_o(sbbiu_dat_sb),
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.sbbiu_adr_o(sbbiu_adr_sb),
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.sbbiu_cyc_o(sbbiu_cyc_sb),
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.sbbiu_stb_o(sbbiu_stb_sb),
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.sbbiu_we_o(sbbiu_we_sb),
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.sbbiu_sel_o(sbbiu_sel_sb),
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.sbbiu_cab_o(sbbiu_cab_sb),
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.sbbiu_dat_i(sbbiu_dat_biu),
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.sbbiu_ack_i(sbbiu_ack_biu),
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.sbbiu_err_i(sbbiu_err_biu)
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);
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);
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//
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//
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// Instantiation of Debug Unit
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// Instantiation of Debug Unit
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//
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//
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