Line 20... |
Line 20... |
//// - Avant! Two-Port Sync RAM (*) ////
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//// - Avant! Two-Port Sync RAM (*) ////
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//// - Virage 2-port Sync RAM ////
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//// - Virage 2-port Sync RAM ////
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//// ////
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//// ////
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//// Supported FPGA RAMs are: ////
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//// Supported FPGA RAMs are: ////
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//// - Xilinx Virtex RAMB4_S16_S16 ////
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//// - Xilinx Virtex RAMB4_S16_S16 ////
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//// - Altera LPM ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - fix Avant! ////
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//// - fix Avant! ////
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//// - xilinx rams need external tri-state logic ////
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//// - xilinx rams need external tri-state logic ////
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//// - add additional RAMs (Altera, VS etc) ////
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//// - add additional RAMs (VS etc) ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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Line 59... |
Line 60... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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|
// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.7 2001/10/21 17:57:16 lampret
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// Revision 1.7 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.6 2001/10/14 13:12:09 lampret
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// Revision 1.6 2001/10/14 13:12:09 lampret
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// MP3 version.
|
// MP3 version.
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Line 249... |
Line 253... |
.DOB(do_b[31:16])
|
.DOB(do_b[31:16])
|
);
|
);
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|
|
`else
|
`else
|
|
|
|
`ifdef OR1200_ALTERA_LPM
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|
|
|
//
|
|
// Instantiation of FPGA memory:
|
|
//
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|
// Altera LPM
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|
//
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|
// Added By Jamil Khatib
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|
//
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|
altqpram altqpram_component (
|
|
.wraddress_a (addr_a),
|
|
.inclocken_a (ce_a),
|
|
.wraddress_b (addr_b),
|
|
.wren_a (we_a),
|
|
.inclocken_b (ce_b),
|
|
.wren_b (we_b),
|
|
.inaclr_a (rst_a),
|
|
.inaclr_b (rst_b),
|
|
.inclock_a (clk_a),
|
|
.inclock_b (clk_b),
|
|
.data_a (di_a),
|
|
.data_b (di_b),
|
|
.q_a (do_a),
|
|
.q_b (do_b)
|
|
);
|
|
|
|
defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",
|
|
altqpram_component.width_write_a = dw,
|
|
altqpram_component.widthad_write_a = aw,
|
|
altqpram_component.numwords_write_a = dw,
|
|
altqpram_component.width_read_a = dw,
|
|
altqpram_component.widthad_read_a = aw,
|
|
altqpram_component.numwords_read_a = dw,
|
|
altqpram_component.width_write_b = dw,
|
|
altqpram_component.widthad_write_b = aw,
|
|
altqpram_component.numwords_write_b = dw,
|
|
altqpram_component.width_read_b = dw,
|
|
altqpram_component.widthad_read_b = aw,
|
|
altqpram_component.numwords_read_b = dw,
|
|
altqpram_component.indata_reg_a = "INCLOCK_A",
|
|
altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",
|
|
altqpram_component.outdata_reg_a = "INCLOCK_A",
|
|
altqpram_component.indata_reg_b = "INCLOCK_B",
|
|
altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",
|
|
altqpram_component.outdata_reg_b = "INCLOCK_B",
|
|
altqpram_component.indata_aclr_a = "INACLR_A",
|
|
altqpram_component.wraddress_aclr_a = "INACLR_A",
|
|
altqpram_component.wrcontrol_aclr_a = "INACLR_A",
|
|
altqpram_component.outdata_aclr_a = "INACLR_A",
|
|
altqpram_component.indata_aclr_b = "NONE",
|
|
altqpram_component.wraddress_aclr_b = "NONE",
|
|
altqpram_component.wrcontrol_aclr_b = "NONE",
|
|
altqpram_component.outdata_aclr_b = "INACLR_B",
|
|
altqpram_component.lpm_hint = "USE_ESB=ON";
|
|
//examplar attribute altqpram_component NOOPT TRUE
|
|
|
|
`else
|
|
|
//
|
//
|
// Generic two-port synchronous RAM model
|
// Generic two-port synchronous RAM model
|
//
|
//
|
|
|
//
|
//
|
Line 263... |
Line 325... |
reg [dw-1:0] do_reg_b; // RAM data output register
|
reg [dw-1:0] do_reg_b; // RAM data output register
|
|
|
//
|
//
|
// Data output drivers
|
// Data output drivers
|
//
|
//
|
assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};
|
assign do_a = (oe_a) ? do_reg_a : {dw{1'b0}};
|
assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};
|
assign do_b = (oe_b) ? do_reg_b : {dw{1'b0}};
|
|
|
//
|
//
|
// RAM read and write
|
// RAM read and write
|
//
|
//
|
always @(posedge clk_a)
|
always @(posedge clk_a)
|
Line 284... |
Line 346... |
if (ce_b && !we_b)
|
if (ce_b && !we_b)
|
do_reg_b <= #1 mem[addr_b];
|
do_reg_b <= #1 mem[addr_b];
|
else if (ce_b && we_b)
|
else if (ce_b && we_b)
|
mem[addr_b] <= #1 di_b;
|
mem[addr_b] <= #1 di_b;
|
|
|
|
`endif // !OR1200_ALTERA_LPM
|
`endif // !OR1200_XILINX_RAMB4_S16_S16
|
`endif // !OR1200_XILINX_RAMB4_S16_S16
|
`endif // !OR1200_VIRAGE_STP
|
`endif // !OR1200_VIRAGE_STP
|
`endif // !OR1200_AVANT_ATP
|
`endif // !OR1200_AVANT_ATP
|
`endif // !OR1200_ARTISAN_SDP
|
`endif // !OR1200_ARTISAN_SDP
|
|
|