| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/08/18 19:54:47 lampret
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// Added store buffer.
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//
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// Revision 1.4 2002/02/11 04:33:17 lampret
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// Revision 1.4 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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| Line 99... |
Line 102... |
dc_en,
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dc_en,
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dcdmmu_adr_i, dcdmmu_cycstb_i, dcdmmu_ci_i,
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dcdmmu_adr_i, dcdmmu_cycstb_i, dcdmmu_ci_i,
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dcpu_we_i, dcpu_sel_i, dcpu_tag_i, dcpu_dat_i,
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dcpu_we_i, dcpu_sel_i, dcpu_tag_i, dcpu_dat_i,
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dcpu_dat_o, dcpu_ack_o, dcpu_rty_o, dcdmmu_err_o, dcdmmu_tag_o,
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dcpu_dat_o, dcpu_ack_o, dcpu_rty_o, dcdmmu_err_o, dcdmmu_tag_o,
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`ifdef OR1200_BIST
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// RAM BIST
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scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
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`endif
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// SPRs
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// SPRs
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spr_cs, spr_write, spr_dat_i
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spr_cs, spr_write, spr_dat_i
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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| Line 146... |
Line 154... |
output dcpu_ack_o;
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output dcpu_ack_o;
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output dcpu_rty_o;
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output dcpu_rty_o;
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output dcdmmu_err_o;
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output dcdmmu_err_o;
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output [3:0] dcdmmu_tag_o;
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output [3:0] dcdmmu_tag_o;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input scanb_rst,
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scanb_si,
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scanb_en,
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scanb_clk;
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output scanb_so;
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`endif
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//
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//
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// SPR access
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// SPR access
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//
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//
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input spr_cs;
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input spr_cs;
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input spr_write;
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input spr_write;
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| Line 176... |
Line 195... |
wire dcfsm_first_hit_ack;
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wire dcfsm_first_hit_ack;
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wire dcfsm_first_miss_ack;
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wire dcfsm_first_miss_ack;
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wire dcfsm_first_miss_err;
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wire dcfsm_first_miss_err;
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wire dcfsm_burst;
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wire dcfsm_burst;
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wire dcfsm_tag_we;
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wire dcfsm_tag_we;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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wire scanb_ram_so;
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wire scanb_tag_so;
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wire scanb_ram_si = scanb_si;
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wire scanb_tag_si = scanb_ram_so;
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assign scanb_so = scanb_tag_so;
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`endif
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//
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//
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// Simple assignments
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// Simple assignments
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//
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//
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assign dcsb_adr_o = dc_addr;
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assign dcsb_adr_o = dc_addr;
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| Line 268... |
Line 297... |
// Instantiation of DC main memory
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// Instantiation of DC main memory
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//
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//
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or1200_dc_ram or1200_dc_ram(
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or1200_dc_ram or1200_dc_ram(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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`ifdef OR1200_BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_ram_si),
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.scanb_so(scanb_ram_so),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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.addr(dc_addr[`OR1200_DCINDXH:2]),
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.addr(dc_addr[`OR1200_DCINDXH:2]),
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.en(dc_en),
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.en(dc_en),
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.we(dcram_we),
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.we(dcram_we),
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.datain(to_dcram),
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.datain(to_dcram),
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.dataout(from_dcram)
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.dataout(from_dcram)
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| Line 281... |
Line 318... |
// Instantiation of DC TAG memory
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// Instantiation of DC TAG memory
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//
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//
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or1200_dc_tag or1200_dc_tag(
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or1200_dc_tag or1200_dc_tag(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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`ifdef OR1200_BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_tag_si),
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.scanb_so(scanb_tag_so),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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.addr(dctag_addr),
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.addr(dctag_addr),
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.en(dctag_en),
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.en(dctag_en),
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.we(dctag_we),
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.we(dctag_we),
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.datain({dc_addr[31:`OR1200_DCTAGL], dctag_v}),
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.datain({dc_addr[31:`OR1200_DCTAGL], dctag_v}),
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.tag_v(tag_v),
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.tag_v(tag_v),
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