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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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Line 90... |
module or1200_dc_top(
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module or1200_dc_top(
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// Rst, clk and clock control
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// Rst, clk and clock control
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clk, rst,
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clk, rst,
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// External i/f
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// External i/f
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dcbiu_dat_o, dcbiu_adr_o, dcbiu_cyc_o, dcbiu_stb_o, dcbiu_we_o, dcbiu_sel_o, dcbiu_cab_o,
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dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o, dcsb_cab_o,
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dcbiu_dat_i, dcbiu_ack_i, dcbiu_err_i,
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dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
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// Internal i/f
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// Internal i/f
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dc_en,
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dc_en,
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dcdmmu_adr_i, dcdmmu_cycstb_i, dcdmmu_ci_i,
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dcdmmu_adr_i, dcdmmu_cycstb_i, dcdmmu_ci_i,
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dcpu_we_i, dcpu_sel_i, dcpu_tag_i, dcpu_dat_i,
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dcpu_we_i, dcpu_sel_i, dcpu_tag_i, dcpu_dat_i,
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| Line 115... |
Line 118... |
input rst;
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input rst;
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//
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//
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// External I/F
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// External I/F
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//
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//
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output [dw-1:0] dcbiu_dat_o;
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output [dw-1:0] dcsb_dat_o;
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output [31:0] dcbiu_adr_o;
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output [31:0] dcsb_adr_o;
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output dcbiu_cyc_o;
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output dcsb_cyc_o;
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output dcbiu_stb_o;
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output dcsb_stb_o;
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output dcbiu_we_o;
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output dcsb_we_o;
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output [3:0] dcbiu_sel_o;
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output [3:0] dcsb_sel_o;
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output dcbiu_cab_o;
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output dcsb_cab_o;
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input [dw-1:0] dcbiu_dat_i;
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input [dw-1:0] dcsb_dat_i;
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input dcbiu_ack_i;
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input dcsb_ack_i;
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input dcbiu_err_i;
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input dcsb_err_i;
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//
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//
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// Internal I/F
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// Internal I/F
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//
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//
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input dc_en;
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input dc_en;
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| Line 177... |
Line 180... |
wire dcfsm_tag_we;
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wire dcfsm_tag_we;
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//
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//
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// Simple assignments
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// Simple assignments
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//
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//
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assign dcbiu_adr_o = dc_addr;
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assign dcsb_adr_o = dc_addr;
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assign dc_inv = spr_cs & spr_write;
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assign dc_inv = spr_cs & spr_write;
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assign dctag_we = dcfsm_tag_we | dc_inv;
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assign dctag_we = dcfsm_tag_we | dc_inv;
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assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
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assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
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assign dctag_en = dc_inv | dc_en;
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assign dctag_en = dc_inv | dc_en;
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assign dctag_v = ~dc_inv;
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assign dctag_v = ~dc_inv;
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//
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//
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// Data to BIU is from DCRAM when DC is enabled or from LSU when
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// Data to BIU is from DCRAM when DC is enabled or from LSU when
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// DC is disabled
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// DC is disabled
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//
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//
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assign dcbiu_dat_o = dcpu_dat_i;
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assign dcsb_dat_o = dcpu_dat_i;
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//
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//
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// Bypases of the DC when DC is disabled
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// Bypases of the DC when DC is disabled
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//
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//
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assign dcbiu_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
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assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
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assign dcbiu_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
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assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
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assign dcbiu_we_o = (dc_en) ? dcfsm_biu_write : dcpu_we_i;
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assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcpu_we_i;
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assign dcbiu_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcdmmu_ci_i) ? 4'b1111 : dcpu_sel_i;
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assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcdmmu_ci_i) ? 4'b1111 : dcpu_sel_i;
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assign dcbiu_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
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assign dcsb_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
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assign dcpu_rty_o = ~dcpu_ack_o;
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assign dcpu_rty_o = ~dcpu_ack_o;
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assign dcdmmu_tag_o = dcdmmu_err_o ? `OR1200_DTAG_BE : dcpu_tag_i;
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assign dcdmmu_tag_o = dcdmmu_err_o ? `OR1200_DTAG_BE : dcpu_tag_i;
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//
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//
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// DC/LSU normal and error termination
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// DC/LSU normal and error termination
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//
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//
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assign dcpu_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcbiu_ack_i;
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assign dcpu_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
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assign dcdmmu_err_o = dc_en ? dcfsm_first_miss_err : dcbiu_err_i;
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assign dcdmmu_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
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//
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//
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// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
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// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
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//
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//
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//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcdmmu_adr_i;
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//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcdmmu_adr_i;
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//
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//
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// Select between input data generated by LSU or by BIU
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// Select between input data generated by LSU or by BIU
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//
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//
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assign to_dcram = (dcfsm_biu_read) ? dcbiu_dat_i : dcpu_dat_i;
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assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcpu_dat_i;
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//
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//
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// Select between data generated by DCRAM or passed by BIU
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// Select between data generated by DCRAM or passed by BIU
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//
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//
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assign dcpu_dat_o = dcfsm_first_miss_ack | !dc_en ? dcbiu_dat_i : from_dcram;
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assign dcpu_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
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//
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//
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// Tag comparison
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// Tag comparison
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//
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//
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always @(tag or saved_addr or tag_v) begin
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always @(tag or saved_addr or tag_v) begin
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| Line 244... |
Line 247... |
.dcdmmu_cycstb_i(dcdmmu_cycstb_i),
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.dcdmmu_cycstb_i(dcdmmu_cycstb_i),
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.dcdmmu_ci_i(dcdmmu_ci_i),
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.dcdmmu_ci_i(dcdmmu_ci_i),
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.dcpu_we_i(dcpu_we_i),
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.dcpu_we_i(dcpu_we_i),
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.dcpu_sel_i(dcpu_sel_i),
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.dcpu_sel_i(dcpu_sel_i),
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.tagcomp_miss(tagcomp_miss),
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.tagcomp_miss(tagcomp_miss),
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.biudata_valid(dcbiu_ack_i),
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.biudata_valid(dcsb_ack_i),
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.biudata_error(dcbiu_err_i),
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.biudata_error(dcsb_err_i),
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.start_addr(dcdmmu_adr_i),
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.start_addr(dcdmmu_adr_i),
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.saved_addr(saved_addr),
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.saved_addr(saved_addr),
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.dcram_we(dcram_we),
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.dcram_we(dcram_we),
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.biu_read(dcfsm_biu_read),
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.biu_read(dcfsm_biu_read),
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.biu_write(dcfsm_biu_write),
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.biu_write(dcfsm_biu_write),
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