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Rev 1038 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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// Revision 1.6 2002/03/14 00:30:24 lampret
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// Revision 1.6 2002/03/14 00:30:24 lampret
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// Added alternative for critical path in DU.
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// Added alternative for critical path in DU.
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//
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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//
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// Read DU registers
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// Read DU registers
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//
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//
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`ifdef OR1200_DU_READREGS
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`ifdef OR1200_DU_READREGS
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always @(spr_addr or dsr or drr or dmr1 or dmr2 or
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always @(spr_addr or dsr or drr or dmr1 or dmr2 or
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tbia_dat_o or tbim_dat_o or tbar_dat_o or tb_wadr)
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tbia_dat_o or tbim_dat_o or tbar_dat_o
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`ifdef OR1200_DU_TB_IMPLEMENTED
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or tb_wadr
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`endif
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)
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casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
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casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
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`ifdef OR1200_DU_DMR1
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`ifdef OR1200_DU_DMR1
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`OR1200_DU_OFS_DMR1:
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`OR1200_DU_OFS_DMR1:
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spr_dat_o = {8'b0, dmr1, 22'b0};
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spr_dat_o = {8'b0, dmr1, 22'b0};
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`endif
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`endif
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