URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_22/] [or1200/] [rtl/] [verilog/] [or1200_tpram_32x32.v] - Diff between revs 1163 and 1171

Rev 1163	Rev 1171
Line 60...	Line 60...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2003/04/07 01:19:07 lampret`
	`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
`//`	`//`
`// Revision 1.7 2001/10/21 17:57:16 lampret`	`// Revision 1.7 2001/10/21 17:57:16 lampret`
`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`	`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
Line 253...	Line 256...
`.DOB(do_b[31:16])`	`.DOB(do_b[31:16])`
`);`	`);`

`else	`else

`ifdef OR1200_ALTERA_LPM	`ifdef OR1200_ALTERA_LPM_XXX

`//`	`//`
`// Instantiation of FPGA memory:`	`// Instantiation of FPGA memory:`
`//`	`//`
`// Altera LPM`	`// Altera LPM`