| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/09/07 05:42:02 lampret
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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//
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// Revision 1.6 2002/03/29 15:16:54 lampret
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// Revision 1.6 2002/03/29 15:16:54 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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//
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//
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// Revision 1.5 2002/02/01 19:56:54 lampret
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// Revision 1.5 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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// Fixed combinational loops.
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| Line 161... |
Line 164... |
// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op;
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reg [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op;
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reg [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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reg [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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reg [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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reg [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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`ifdef OR1200_MAC_IMPLEMENTED
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op;
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reg ex_macrc_op;
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`else
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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wire ex_macrc_op;
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`endif
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reg [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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reg [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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reg [31:0] id_insn;
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reg [31:0] id_insn;
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reg [31:0] ex_insn;
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reg [31:0] ex_insn;
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reg [31:0] wb_insn;
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reg [31:0] wb_insn;
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reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
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reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
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| Line 181... |
Line 190... |
reg imm_signextend;
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reg imm_signextend;
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reg [15:0] spr_addrimm;
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reg [15:0] spr_addrimm;
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reg sig_syscall;
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reg sig_syscall;
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reg sig_trap;
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reg sig_trap;
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reg except_illegal;
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reg except_illegal;
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reg ex_macrc_op;
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wire id_void;
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wire id_void;
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//
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//
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// Register file read addresses
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// Register file read addresses
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//
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//
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| Line 216... |
Line 224... |
assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};
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assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};
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//
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//
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// l.macrc in ID stage
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// l.macrc in ID stage
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//
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//
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`ifdef OR1200_MAC_IMPLEMENTED
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assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MOVHI) & id_insn[16];
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assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MOVHI) & id_insn[16];
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`else
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assign id_macrc_op = 1'b0;
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`endif
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//
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//
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//
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//
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//
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//
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assign rfe = (pre_branch_op == `OR1200_BRANCHOP_RFE) | (branch_op == `OR1200_BRANCHOP_RFE);
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assign rfe = (pre_branch_op == `OR1200_BRANCHOP_RFE) | (branch_op == `OR1200_BRANCHOP_RFE);
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| Line 250... |
Line 262... |
sel_b = `OR1200_SEL_RF;
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sel_b = `OR1200_SEL_RF;
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//
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//
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// l.macrc in EX stage
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// l.macrc in EX stage
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//
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//
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`ifdef OR1200_MAC_IMPLEMENTED
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst)
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if (rst)
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ex_macrc_op <= #1 1'b0;
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ex_macrc_op <= #1 1'b0;
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else if (!ex_freeze & id_freeze | flushpipe)
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else if (!ex_freeze & id_freeze | flushpipe)
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ex_macrc_op <= #1 1'b0;
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ex_macrc_op <= #1 1'b0;
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else if (!ex_freeze)
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else if (!ex_freeze)
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ex_macrc_op <= #1 id_macrc_op;
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ex_macrc_op <= #1 id_macrc_op;
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end
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end
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`else
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assign ex_macrc_op = 1'b0;
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`endif
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//
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//
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// Decode of spr_addrimm
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// Decode of spr_addrimm
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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| Line 349... |
Line 365... |
// l.xori
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// l.xori
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`OR1200_OR32_XORI:
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`OR1200_OR32_XORI:
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imm_signextend = 1'b1;
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imm_signextend = 1'b1;
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// l.muli
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// l.muli
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`ifdef OR1200_MULT_IMPLEMENTED
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`OR1200_OR32_MULI:
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`OR1200_OR32_MULI:
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imm_signextend = 1'b1;
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imm_signextend = 1'b1;
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`endif
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// l.maci
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// l.maci
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`ifdef OR1200_MAC_IMPLEMENTED
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`OR1200_OR32_MACI:
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`OR1200_OR32_MACI:
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imm_signextend = 1'b1;
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imm_signextend = 1'b1;
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`endif
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// SFXX insns with immediate
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// SFXX insns with immediate
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`OR1200_OR32_SFXXI:
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`OR1200_OR32_SFXXI:
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imm_signextend = 1'b1;
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imm_signextend = 1'b1;
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| Line 492... |
Line 512... |
// l.sys, l.brk and all three sync insns
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// l.sys, l.brk and all three sync insns
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`OR1200_OR32_XSYNC:
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`OR1200_OR32_XSYNC:
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sel_imm <= #1 1'b0;
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sel_imm <= #1 1'b0;
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// l.mac/l.msb
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// l.mac/l.msb
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`ifdef OR1200_MAC_IMPLEMENTED
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`OR1200_OR32_MACMSB:
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`OR1200_OR32_MACMSB:
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sel_imm <= #1 1'b0;
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sel_imm <= #1 1'b0;
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`endif
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// l.sw
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// l.sw
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`OR1200_OR32_SW:
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`OR1200_OR32_SW:
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sel_imm <= #1 1'b0;
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sel_imm <= #1 1'b0;
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| Line 550... |
Line 572... |
`OR1200_OR32_BF,
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`OR1200_OR32_BF,
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`OR1200_OR32_RFE,
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`OR1200_OR32_RFE,
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`OR1200_OR32_MOVHI,
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`OR1200_OR32_MOVHI,
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`OR1200_OR32_MFSPR,
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`OR1200_OR32_MFSPR,
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`OR1200_OR32_XSYNC,
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`OR1200_OR32_XSYNC,
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`ifdef OR1200_MAC_IMPLEMENTED
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`OR1200_OR32_MACI,
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`OR1200_OR32_MACI,
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`endif
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`OR1200_OR32_LWZ,
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`OR1200_OR32_LWZ,
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`OR1200_OR32_LBZ,
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`OR1200_OR32_LBZ,
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`OR1200_OR32_LBS,
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`OR1200_OR32_LBS,
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`OR1200_OR32_LHZ,
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`OR1200_OR32_LHZ,
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`OR1200_OR32_LHS,
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`OR1200_OR32_LHS,
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`OR1200_OR32_ADDI,
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`OR1200_OR32_ADDI,
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`OR1200_OR32_ADDIC,
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`OR1200_OR32_ADDIC,
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`OR1200_OR32_ANDI,
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`OR1200_OR32_ANDI,
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`OR1200_OR32_ORI,
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`OR1200_OR32_ORI,
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`OR1200_OR32_XORI,
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`OR1200_OR32_XORI,
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`ifdef OR1200_MULT_IMPLEMENTED
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`OR1200_OR32_MULI,
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`OR1200_OR32_MULI,
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`endif
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`OR1200_OR32_SH_ROTI,
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`OR1200_OR32_SH_ROTI,
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`OR1200_OR32_SFXXI,
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`OR1200_OR32_SFXXI,
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`OR1200_OR32_MTSPR,
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`OR1200_OR32_MTSPR,
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`ifdef OR1200_MAC_IMPLEMENTED
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`OR1200_OR32_MACMSB,
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`OR1200_OR32_MACMSB,
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`endif
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`OR1200_OR32_SW,
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`OR1200_OR32_SW,
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`OR1200_OR32_SB,
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`OR1200_OR32_SB,
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`OR1200_OR32_SH,
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`OR1200_OR32_SH,
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`OR1200_OR32_ALU,
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`OR1200_OR32_ALU,
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`OR1200_OR32_SFXX,
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`OR1200_OR32_SFXX,
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| Line 643... |
Line 671... |
// l.xori
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// l.xori
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`OR1200_OR32_XORI:
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`OR1200_OR32_XORI:
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alu_op <= #1 `OR1200_ALUOP_XOR;
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alu_op <= #1 `OR1200_ALUOP_XOR;
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// l.muli
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// l.muli
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`ifdef OR1200_MULT_IMPLEMENTED
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`OR1200_OR32_MULI:
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`OR1200_OR32_MULI:
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alu_op <= #1 `OR1200_ALUOP_MUL;
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alu_op <= #1 `OR1200_ALUOP_MUL;
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`endif
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// Shift and rotate insns with immediate
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// Shift and rotate insns with immediate
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`OR1200_OR32_SH_ROTI:
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`OR1200_OR32_SH_ROTI:
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alu_op <= #1 `OR1200_ALUOP_SHROT;
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alu_op <= #1 `OR1200_ALUOP_SHROT;
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| Line 675... |
Line 705... |
end
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end
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//
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//
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// Decode of mac_op
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// Decode of mac_op
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//
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//
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`ifdef OR1200_MAC_IMPLEMENTED
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst)
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if (rst)
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mac_op <= #1 `OR1200_MACOP_NOP;
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mac_op <= #1 `OR1200_MACOP_NOP;
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else if (!ex_freeze & id_freeze | flushpipe)
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else if (!ex_freeze & id_freeze | flushpipe)
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mac_op <= #1 `OR1200_MACOP_NOP;
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mac_op <= #1 `OR1200_MACOP_NOP;
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| Line 700... |
Line 731... |
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endcase
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endcase
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else
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else
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mac_op <= #1 `OR1200_MACOP_NOP;
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mac_op <= #1 `OR1200_MACOP_NOP;
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end
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end
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`else
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assign mac_op = `OR1200_MACOP_NOP;
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`endif
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//
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//
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// Decode of shrot_op
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// Decode of shrot_op
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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| Line 782... |
Line 816... |
// l.xori
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// l.xori
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`OR1200_OR32_XORI:
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`OR1200_OR32_XORI:
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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// l.muli
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// l.muli
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`ifdef OR1200_MULT_IMPLEMENTED
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`OR1200_OR32_MULI:
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`OR1200_OR32_MULI:
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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`endif
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// Shift and rotate insns with immediate
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// Shift and rotate insns with immediate
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`OR1200_OR32_SH_ROTI:
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`OR1200_OR32_SH_ROTI:
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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