| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.8 2001/10/19 23:28:46 lampret
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// Revision 1.8 2001/10/19 23:28:46 lampret
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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| Line 189... |
Line 192... |
if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // load aborted (usually caused by DMMU)
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if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // load aborted (usually caused by DMMU)
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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else if (biudata_error) begin // load terminated with an error
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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end
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else if (dcdmmu_ci_i & biudata_valid) begin // load from cache inhibit page
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else if (dcdmmu_ci_i & biudata_valid) begin // load from cache inhibit page
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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| Line 223... |
Line 231... |
if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // store aborted (usually caused by DMMU)
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if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // store aborted (usually caused by DMMU)
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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end
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end
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else if (biudata_error) begin // store terminated with an error
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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end
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else if (dcdmmu_ci_i & biudata_valid) begin // store to cache inhibit page
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else if (dcdmmu_ci_i & biudata_valid) begin // store to cache inhibit page
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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end
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end
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