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[/] [or1k/] [tags/] [rel_23/] [or1200/] [rtl/] [verilog/] [or1200_dc_ram.v] - Diff between revs 1163 and 1214

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Rev 1163	Rev 1214
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2002/10/17 20:04:40 lampret`
	`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
`//`	`//`
`// Revision 1.8 2001/10/21 17:57:16 lampret`	`// Revision 1.8 2001/10/21 17:57:16 lampret`
`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`	`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
Line 74...	Line 77...
`// Reset and clock`	`// Reset and clock`
`clk, rst,`	`clk, rst,`

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
`endif	`endif

`// Internal i/f`	`// Internal i/f`
`addr, en, we, datain, dataout`	`addr, en, we, datain, dataout`
`);`	`);`
Line 99...	Line 102...

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`//`	`//`
`// RAM BIST`	`// RAM BIST`
`//`	`//`
`input scanb_rst,`	`input mbist_si_i;`
`scanb_si,`	input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
`scanb_en,`	`output mbist_so_o;`
`scanb_clk;`
`output scanb_so;`
`endif	`endif

`ifdef OR1200_NO_DC	`ifdef OR1200_NO_DC

`//`	`//`
`// Data cache not implemented`	`// Data cache not implemented`
`//`	`//`
`assign dataout = {dw{1'b0}};`	`assign dataout = {dw{1'b0}};`
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`assign scanb_so = scanb_si;`	`assign mbist_so_o = mbist_si_i;`
`endif	`endif

`else	`else

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`//`	`//`
`// RAM BIST`	`// RAM BIST`
`//`	`//`
`wire scanb_ram0_so;`	`wire mbist_ram0_so;`
`wire scanb_ram1_so;`	`wire mbist_ram1_so;`
`wire scanb_ram2_so;`	`wire mbist_ram2_so;`
`wire scanb_ram3_so;`	`wire mbist_ram3_so;`
`wire scanb_ram0_si = scanb_si;`	`wire mbist_ram0_si = mbist_si_i;`
`wire scanb_ram1_si = scanb_ram0_so;`	`wire mbist_ram1_si = mbist_ram0_so;`
`wire scanb_ram2_si = scanb_ram1_so;`	`wire mbist_ram2_si = mbist_ram1_so;`
`wire scanb_ram3_si = scanb_ram2_so;`	`wire mbist_ram3_si = mbist_ram2_so;`
`assign scanb_so = scanb_ram3_so;`	`assign mbist_so_o = mbist_ram3_so;`
`endif	`endif

`//`	`//`
`// Instantiation of RAM block 0`	`// Instantiation of RAM block 0`
`//`	`//`
Line 144...	Line 145...
`ifdef OR1200_DC_1W_8KB	`ifdef OR1200_DC_1W_8KB
`or1200_spram_2048x8 dc_ram0(`	`or1200_spram_2048x8 dc_ram0(`
`endif	`endif
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.scanb_rst(scanb_rst),`	`.mbist_si_i(mbist_ram0_si),`
`.scanb_si(scanb_ram0_si),`	`.mbist_so_o(mbist_ram0_so),`
`.scanb_so(scanb_ram0_so),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`.scanb_en(scanb_en),`
`.scanb_clk(scanb_clk),`
`endif	`endif
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.ce(en),`	`.ce(en),`
`.we(we[0]),`	`.we(we[0]),`
Line 171...	Line 170...
`ifdef OR1200_DC_1W_8KB	`ifdef OR1200_DC_1W_8KB
`or1200_spram_2048x8 dc_ram1(`	`or1200_spram_2048x8 dc_ram1(`
`endif	`endif
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.scanb_rst(scanb_rst),`	`.mbist_si_i(mbist_ram1_si),`
`.scanb_si(scanb_ram1_si),`	`.mbist_so_o(mbist_ram1_so),`
`.scanb_so(scanb_ram1_so),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`.scanb_en(scanb_en),`
`.scanb_clk(scanb_clk),`
`endif	`endif
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.ce(en),`	`.ce(en),`
`.we(we[1]),`	`.we(we[1]),`
Line 198...	Line 195...
`ifdef OR1200_DC_1W_8KB	`ifdef OR1200_DC_1W_8KB
`or1200_spram_2048x8 dc_ram2(`	`or1200_spram_2048x8 dc_ram2(`
`endif	`endif
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.scanb_rst(scanb_rst),`	`.mbist_si_i(mbist_ram2_si),`
`.scanb_si(scanb_ram2_si),`	`.mbist_so_o(mbist_ram2_so),`
`.scanb_so(scanb_ram2_so),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`.scanb_en(scanb_en),`
`.scanb_clk(scanb_clk),`
`endif	`endif
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.ce(en),`	`.ce(en),`
`.we(we[2]),`	`.we(we[2]),`
Line 225...	Line 220...
`ifdef OR1200_DC_1W_8KB	`ifdef OR1200_DC_1W_8KB
`or1200_spram_2048x8 dc_ram3(`	`or1200_spram_2048x8 dc_ram3(`
`endif	`endif
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.scanb_rst(scanb_rst),`	`.mbist_si_i(mbist_ram3_si),`
`.scanb_si(scanb_ram3_si),`	`.mbist_so_o(mbist_ram3_so),`
`.scanb_so(scanb_ram3_so),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`.scanb_en(scanb_en),`
`.scanb_clk(scanb_clk),`
`endif	`endif
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.ce(en),`	`.ce(en),`
`.we(we[3]),`	`.we(we[3]),`

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[/] [or1k/] [tags/] [rel_23/] [or1200/] [rtl/] [verilog/] [or1200_dc_ram.v] - Diff between revs 1163 and 1214