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[/] [or1k/] [tags/] [rel_23/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Diff between revs 1163 and 1171
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Rev 1171 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2003/04/07 01:19:07 lampret
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// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
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//
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// Revision 1.6 2002/03/28 19:25:42 lampret
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// Revision 1.6 2002/03/28 19:25:42 lampret
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// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
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// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
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//
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//
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// Revision 1.5 2002/02/01 19:56:54 lampret
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// Revision 1.5 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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// Fixed combinational loops.
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.DOB()
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.DOB()
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);
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);
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`else
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`else
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`ifdef OR1200_ALTERA_LPM
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`ifdef OR1200_ALTERA_LPM_XXX
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//
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//
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// Instantiation of FPGA memory:
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// Instantiation of FPGA memory:
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//
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//
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// Altera LPM
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// Altera LPM
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