URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_23/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Diff between revs 1163 and 1171

Rev 1163	Rev 1171
Line 60...	Line 60...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.7 2003/04/07 01:19:07 lampret`
	`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
	`//`
`// Revision 1.6 2002/03/28 19:25:42 lampret`	`// Revision 1.6 2002/03/28 19:25:42 lampret`
`// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.`	`// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.`
`//`	`//`
`// Revision 1.5 2002/02/01 19:56:54 lampret`	`// Revision 1.5 2002/02/01 19:56:54 lampret`
`// Fixed combinational loops.`	`// Fixed combinational loops.`
Line 400...	Line 403...
`.DOB()`	`.DOB()`
`);`	`);`

`else	`else

`ifdef OR1200_ALTERA_LPM	`ifdef OR1200_ALTERA_LPM_XXX

`//`	`//`
`// Instantiation of FPGA memory:`	`// Instantiation of FPGA memory:`
`//`	`//`
`// Altera LPM`	`// Altera LPM`