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[/] [or1k/] [tags/] [rel_23/] [or1200/] [rtl/] [verilog/] [or1200_immu_top.v] - Diff between revs 660 and 788

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Rev 660 Rev 788
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.5  2002/02/11 04:33:17  lampret
 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
 
//
// Revision 1.4  2002/02/01 19:56:54  lampret
// Revision 1.4  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
// Fixed combinational loops.
//
//
// Revision 1.3  2002/01/28 01:16:00  lampret
// Revision 1.3  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
Line 158... Line 161...
wire                            itlb_ci;
wire                            itlb_ci;
wire                            itlb_done;
wire                            itlb_done;
wire                            fault;
wire                            fault;
wire                            miss;
wire                            miss;
reg     [31:0]                   icpu_adr_o;
reg     [31:0]                   icpu_adr_o;
 
`ifdef OR1200_NO_IMMU
 
`else
reg                             itlb_en_r;
reg                             itlb_en_r;
reg     [31:`OR1200_IMMU_PS]    icpu_vpn_r;
reg     [31:`OR1200_IMMU_PS]    icpu_vpn_r;
 
`endif
 
 
//
//
// Implemented bits inside match and translate registers
// Implemented bits inside match and translate registers
//
//
// itlbwYmrX: vpn 31-10  v 0
// itlbwYmrX: vpn 31-10  v 0

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