| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/08/12 05:31:30 lampret
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// Delayed external access at page crossing.
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//
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// Revision 1.6 2002/03/29 15:16:56 lampret
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// Revision 1.6 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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//
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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| Line 168... |
Line 171... |
wire page_cross;
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wire page_cross;
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reg [31:0] icpu_adr_o;
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reg [31:0] icpu_adr_o;
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`ifdef OR1200_NO_IMMU
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`ifdef OR1200_NO_IMMU
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`else
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`else
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reg itlb_en_r;
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reg itlb_en_r;
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reg dis_spr_access;
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reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
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reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
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`endif
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`endif
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//
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//
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// Implemented bits inside match and translate registers
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// Implemented bits inside match and translate registers
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| Line 221... |
Line 225... |
// 1200 - 123F itlbmr w0 [63:0]
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// 1200 - 123F itlbmr w0 [63:0]
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//
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//
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// 1300 - 13FF itlbtr w0
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// 1300 - 13FF itlbtr w0
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// 1300 - 133F itlbtr w0 [63:0]
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// 1300 - 133F itlbtr w0 [63:0]
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//
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//
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assign itlb_spr_access = spr_cs;
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assign itlb_spr_access = spr_cs & ~dis_spr_access;
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//
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// Disable ITLB SPR access
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//
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// This flop is used to mask ITLB miss/fault exception
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// during first clock cycle of accessing ITLB SPR. In
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// subsequent clock cycles it is assumed that ITLB SPR
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// access was accomplished and that normal instruction fetching
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// can proceed.
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//
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// spr_cs sets dis_spr_access and icpu_rty_o clears it.
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//
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always @(posedge clk or posedge rst)
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if (rst)
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dis_spr_access <= #1 1'b0;
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else if (!icpu_rty_o)
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dis_spr_access <= #1 1'b0;
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else if (spr_cs)
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dis_spr_access <= #1 1'b1;
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//
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//
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// Tags:
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// Tags:
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//
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//
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// OR1200_DTAG_TE - TLB miss Exception
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// OR1200_DTAG_TE - TLB miss Exception
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| Line 235... |
Line 258... |
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//
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//
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// icpu_rty_o
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// icpu_rty_o
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//
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//
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// assign icpu_rty_o = !icpu_err_o & icimmu_rty_i;
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// assign icpu_rty_o = !icpu_err_o & icimmu_rty_i;
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assign icpu_rty_o = icimmu_rty_i;
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assign icpu_rty_o = icimmu_rty_i | itlb_spr_access;
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//
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//
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// icpu_err_o
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// icpu_err_o
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//
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//
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assign icpu_err_o = miss | fault | icimmu_err_i;
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assign icpu_err_o = miss | fault | icimmu_err_i;
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//
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//
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// Assert itlb_en_r after one clock cycle
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// Assert itlb_en_r after one clock cycle and when there is no
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// ITLB SPR access
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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itlb_en_r <= #1 1'b0;
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itlb_en_r <= #1 1'b0;
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else
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else
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itlb_en_r <= #1 itlb_en;
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itlb_en_r <= #1 itlb_en & ~itlb_spr_access;
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//
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//
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// Assert itlb_done one clock cycle after new address is first presented and tlb is enabled.
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// ITLB lookup successful
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//
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//
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// assign itlb_done = (icpu_adr_i == icpu_adr_o) & itlb_en_r;
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assign itlb_done = itlb_en_r & ~page_cross;
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assign itlb_done = itlb_en_r;
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//
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//
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// Cut transfer if something goes wrong with translation. If IC is disabled,
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// Cut transfer if something goes wrong with translation. If IC is disabled,
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// use delayed signals.
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// use delayed signals.
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//
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//
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| Line 273... |
Line 296... |
//
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//
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// Page cross
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// Page cross
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//
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//
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// Asserted when CPU address crosses page boundary. Most of the time it is zero.
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// Asserted when CPU address crosses page boundary. Most of the time it is zero.
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//
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//
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assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icimmu_adr_o[31:`OR1200_IMMU_PS];
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assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
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//
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//
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// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
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// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
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// one clock cycle after offset part.
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// one clock cycle after offset part.
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//
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//
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| Line 294... |
Line 317... |
assign icimmu_adr_o = immu_en ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]};
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assign icimmu_adr_o = immu_en ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]};
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//
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//
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// Output to SPRS unit
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// Output to SPRS unit
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//
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//
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assign spr_dat_o = itlb_spr_access ? itlb_dat_o : 32'h00000000;
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assign spr_dat_o = spr_cs ? itlb_dat_o : 32'h00000000;
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//
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//
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// Page fault exception logic
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// Page fault exception logic
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//
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//
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assign fault = itlb_done &
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assign fault = itlb_done &
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