OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_23/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Diff between revs 1163 and 1220

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 1163 Rev 1220
Line 42... Line 42...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.9  2002/09/07 05:42:02  lampret
 
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
 
//
// Revision 1.8  2002/08/28 01:44:25  lampret
// Revision 1.8  2002/08/28 01:44:25  lampret
// Removed some commented RTL. Fixed SR/ESR flag bug.
// Removed some commented RTL. Fixed SR/ESR flag bug.
//
//
// Revision 1.7  2002/03/29 15:16:56  lampret
// Revision 1.7  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
// Some of the warnings fixed.
Line 356... Line 359...
//
//
// Supervision register
// Supervision register
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                sr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
                sr <= #1 {1'b1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
        else if (except_started) begin
        else if (except_started) begin
                sr[`OR1200_SR_SM] <= #1 1'b1;
                sr[`OR1200_SR_SM] <= #1 1'b1;
                sr[`OR1200_SR_TEE] <= #1 1'b0;
                sr[`OR1200_SR_TEE] <= #1 1'b0;
                sr[`OR1200_SR_IEE] <= #1 1'b0;
                sr[`OR1200_SR_IEE] <= #1 1'b0;
                sr[`OR1200_SR_DME] <= #1 1'b0;
                sr[`OR1200_SR_DME] <= #1 1'b0;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.