| Line 47... |
Line 47... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2002/09/16 03:09:16 lampret
|
|
// Fixed a combinational loop.
|
|
//
|
// Revision 1.3 2002/08/12 05:31:37 lampret
|
// Revision 1.3 2002/08/12 05:31:37 lampret
|
// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.
|
// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.
|
//
|
//
|
// Revision 1.2 2002/07/14 22:17:17 lampret
|
// Revision 1.2 2002/07/14 22:17:17 lampret
|
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
|
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
|
| Line 96... |
Line 99... |
// RISC clock, reset and clock control
|
// RISC clock, reset and clock control
|
clk, rst, clmode,
|
clk, rst, clmode,
|
|
|
// WISHBONE interface
|
// WISHBONE interface
|
wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
|
wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
|
wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_cab_o, wb_dat_o,
|
wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,
|
|
`ifdef OR1200_WB_CAB
|
|
wb_cab_o,
|
|
`endif
|
|
`ifdef OR1200_WB_B3
|
|
wb_cti_o, wb_bte_o,
|
|
`endif
|
|
|
// Internal RISC bus
|
// Internal RISC bus
|
biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
|
biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
|
biu_dat_o, biu_ack_o, biu_err_o
|
biu_dat_o, biu_ack_o, biu_err_o
|
);
|
);
|
| Line 127... |
Line 136... |
output wb_cyc_o; // cycle valid output
|
output wb_cyc_o; // cycle valid output
|
output [aw-1:0] wb_adr_o; // address bus outputs
|
output [aw-1:0] wb_adr_o; // address bus outputs
|
output wb_stb_o; // strobe output
|
output wb_stb_o; // strobe output
|
output wb_we_o; // indicates write transfer
|
output wb_we_o; // indicates write transfer
|
output [3:0] wb_sel_o; // byte select outputs
|
output [3:0] wb_sel_o; // byte select outputs
|
output wb_cab_o; // consecutive address burst
|
|
output [dw-1:0] wb_dat_o; // output data bus
|
output [dw-1:0] wb_dat_o; // output data bus
|
|
`ifdef OR1200_WB_CAB
|
|
output wb_cab_o; // consecutive address burst
|
|
`endif
|
|
`ifdef OR1200_WB_B3
|
|
output [2:0] wb_cti_o; // cycle type identifier
|
|
output [1:0] wb_bte_o; // burst type extension
|
|
`endif
|
|
|
//
|
//
|
// Internal RISC interface
|
// Internal RISC interface
|
//
|
//
|
input [dw-1:0] biu_dat_i; // input data bus
|
input [dw-1:0] biu_dat_i; // input data bus
|
| Line 154... |
Line 169... |
reg [aw-1:0] wb_adr_o; // address bus outputs
|
reg [aw-1:0] wb_adr_o; // address bus outputs
|
reg wb_cyc_o; // cycle output
|
reg wb_cyc_o; // cycle output
|
reg wb_stb_o; // strobe output
|
reg wb_stb_o; // strobe output
|
reg wb_we_o; // indicates write transfer
|
reg wb_we_o; // indicates write transfer
|
reg [3:0] wb_sel_o; // byte select outputs
|
reg [3:0] wb_sel_o; // byte select outputs
|
|
`ifdef OR1200_WB_CAB
|
reg wb_cab_o; // CAB output
|
reg wb_cab_o; // CAB output
|
|
`endif
|
|
`ifdef OR1200_WB_B3
|
|
reg [1:0] burst_len; // burst counter
|
|
reg [2:0] wb_cti_o; // cycle type identifier
|
|
`endif
|
reg [dw-1:0] wb_dat_o; // output data bus
|
reg [dw-1:0] wb_dat_o; // output data bus
|
`endif
|
`endif
|
`ifdef OR1200_REGISTERED_INPUTS
|
`ifdef OR1200_REGISTERED_INPUTS
|
reg long_ack_o; // normal termination
|
reg long_ack_o; // normal termination
|
reg long_err_o; // error termination
|
reg long_err_o; // error termination
|
| Line 389... |
Line 410... |
wb_sel_o <= #1 biu_sel_i;
|
wb_sel_o <= #1 biu_sel_i;
|
`else
|
`else
|
assign wb_sel_o = biu_sel_i;
|
assign wb_sel_o = biu_sel_i;
|
`endif
|
`endif
|
|
|
|
`ifdef OR1200_WB_CAB
|
//
|
//
|
// WB cab_o
|
// WB cab_o
|
//
|
//
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
| Line 401... |
Line 423... |
else
|
else
|
wb_cab_o <= #1 biu_cab_i;
|
wb_cab_o <= #1 biu_cab_i;
|
`else
|
`else
|
assign wb_cab_o = biu_cab_i;
|
assign wb_cab_o = biu_cab_i;
|
`endif
|
`endif
|
|
`endif
|
|
|
|
`ifdef OR1200_WB_B3
|
|
//
|
|
// Count burst beats
|
|
//
|
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
burst_len <= #1 2'b00;
|
|
else if (biu_cab_i && burst_len && wb_ack_i)
|
|
burst_len <= #1 burst_len - 1'b1;
|
|
else if (~biu_cab_i)
|
|
burst_len <= #1 2'b11;
|
|
|
|
//
|
|
// WB cti_o
|
|
//
|
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
wb_cti_o <= #1 3'b000; // classic cycle
|
|
`ifdef OR1200_NO_BURSTS
|
|
else
|
|
wb_cti_o <= #1 3'b111; // end-of-burst
|
|
`else
|
|
else if (biu_cab_i && burst_len[1])
|
|
wb_cti_o <= #1 3'b010; // incrementing burst cycle
|
|
else if (biu_cab_i && wb_ack_i)
|
|
wb_cti_o <= #1 3'b111; // end-of-burst
|
|
`endif // OR1200_NO_BURSTS
|
|
`else
|
|
Unsupported !!!;
|
|
`endif
|
|
|
|
//
|
|
// WB bte_o
|
|
//
|
|
assign wb_bte_o = 2'b01; // 4-beat wrap burst
|
|
|
|
`endif // OR1200_WB_B3
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
