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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.7 2001/10/21 17:57:16 lampret
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// Revision 1.7 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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| Line 69... |
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_cfgr(
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module or1200_cfgr(
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// RISC Internal Interface
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// RISC Internal Interface
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clk, rst, spr_addr, spr_dat_o
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spr_addr, spr_dat_o
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);
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);
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//
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//
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// RISC Internal Interface
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// RISC Internal Interface
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//
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//
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input clk; // Clock
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input rst; // Reset
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input [31:0] spr_addr; // SPR Address
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input [31:0] spr_addr; // SPR Address
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output [31:0] spr_dat_o; // SPR Read Data
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output [31:0] spr_dat_o; // SPR Read Data
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//
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//
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// Internal wires & registers
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// Internal wires & registers
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