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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 1032 and 1033

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.24  2002/09/07 05:42:02  lampret
 
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
 
//
// Revision 1.23  2002/09/04 00:50:34  lampret
// Revision 1.23  2002/09/04 00:50:34  lampret
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
//
//
// Revision 1.22  2002/09/03 22:28:21  lampret
// Revision 1.22  2002/09/03 22:28:21  lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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//
//
// By default implementation of l.addc/l.addic
// By default implementation of l.addc/l.addic
// instructions and SR[CY] is disabled to save
// instructions and SR[CY] is disabled to save
// area.
// area.
//
//
 
// [Because this define controles implementation
 
//  of SR[CY] write enable, if it is not enabled,
 
//  l.add/l.addi also don't set SR[CY].]
 
//
//`define OR1200_IMPL_ADDC
//`define OR1200_IMPL_ADDC
 
 
//
//
// Implement rotate in the ALU
// Implement rotate in the ALU
//
//

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