| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.6 2002/03/29 15:16:55 lampret
|
|
// Some of the warnings fixed.
|
|
//
|
// Revision 1.5 2002/02/11 04:33:17 lampret
|
// Revision 1.5 2002/02/11 04:33:17 lampret
|
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
|
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
|
//
|
//
|
// Revision 1.4 2002/01/28 01:16:00 lampret
|
// Revision 1.4 2002/01/28 01:16:00 lampret
|
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
|
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
|
| Line 250... |
Line 253... |
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("Starting exception: %h.", except_type);
|
$display("Starting exception: %h.", except_type);
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
pc = { {4{except_prefix}}, 16'h0000, except_type, 8'h00};
|
pc = { {4{except_prefix}}, `OR1200_EXCEPT_MMMM, except_type, `OR1200_EXCEPT_VV};
|
taken = 1'b1;
|
taken = 1'b1;
|
end
|
end
|
default: begin
|
default: begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
| Line 270... |
Line 273... |
//
|
//
|
// PC register
|
// PC register
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
pcreg <= #1 30'd63;
|
// pcreg <= #1 30'd63;
|
|
pcreg <= #1 ({`OR1200_EXCEPT_RESET, `OR1200_EXCEPT_VV} - 1) >> 2;
|
else if (spr_pc_we)
|
else if (spr_pc_we)
|
pcreg <= #1 spr_dat_i[31:2];
|
pcreg <= #1 spr_dat_i[31:2];
|
else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
|
else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
|
// else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
|
// else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
|
pcreg <= #1 pc[31:2];
|
pcreg <= #1 pc[31:2];
|
