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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's generate PC ////
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//// OR1200's generate PC ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// Internal i/f
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// Internal i/f
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branch_op, except_type, except_prefix,
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branch_op, except_type, except_prefix,
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branch_addrofs, lr_restor, flag, taken, except_start,
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branch_addrofs, lr_restor, flag, taken, except_start,
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binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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genpc_freeze, flushpipe
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genpc_freeze, flushpipe, no_more_dslot
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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input spr_pc_we;
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input spr_pc_we;
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input genpc_refetch;
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input genpc_refetch;
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input genpc_freeze;
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input genpc_freeze;
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input flushpipe;
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input flushpipe;
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input no_more_dslot;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [31:2] pcreg;
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reg [31:2] pcreg;
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reg btarget; /* set when fetching branch target insns */
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reg btarget; /* set when fetching branch target insns */
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//
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//
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// Address of insn to be fecthed
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// Address of insn to be fecthed
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//
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//
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assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
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assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
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// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
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//
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//
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// Control access to IC subsystem
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// Control access to IC subsystem
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//
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//
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// assign icpu_cyc_o = !genpc_freeze & !no_more_dslot;
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assign icpu_cyc_o = !genpc_freeze;
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assign icpu_cyc_o = !genpc_freeze;
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assign icpu_stb_o = icpu_cyc_o;
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assign icpu_stb_o = icpu_cyc_o;
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assign icpu_sel_o = 4'b1111;
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assign icpu_sel_o = 4'b1111;
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assign icpu_tag_o = `OR1200_ITAG_NI;
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assign icpu_tag_o = `OR1200_ITAG_NI;
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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pcreg <= #1 30'd63;
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pcreg <= #1 30'd63;
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else if (spr_pc_we)
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else if (spr_pc_we)
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pcreg <= #1 spr_dat_i[31:2];
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pcreg <= #1 spr_dat_i[31:2];
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else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
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else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
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// else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
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pcreg <= #1 pc[31:2];
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pcreg <= #1 pc[31:2];
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//
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// dslot
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//
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always @(posedge clk or posedge rst)
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if (rst)
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dslot <= #1 1'b0;
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else if (spr_pc_we)
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dslot <= #1 1'b0;
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else if (!icpu_rty_i)
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dslot <= #1 |branch_op;
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//
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// btarget
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//
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always @(posedge clk or posedge rst)
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if (rst)
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btarget <= #1 1'b0;
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else if (spr_pc_we)
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btarget <= #1 1'b0;
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else if (!icpu_rty_i)
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btarget <= #1 dslot;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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