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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Data cache state machine ////
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//// Insn cache state machine ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2003/06/06 02:54:47 lampret
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// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
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//
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// Revision 1.7 2002/03/29 15:16:55 lampret
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// Revision 1.7 2002/03/29 15:16:55 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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//
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//
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// Revision 1.6 2002/03/28 19:10:40 lampret
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// Revision 1.6 2002/03/28 19:10:40 lampret
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// Optimized cache controller FSM.
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// Optimized cache controller FSM.
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module or1200_ic_fsm(
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module or1200_ic_fsm(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// Internal i/f to top level IC
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// Internal i/f to top level IC
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ic_en, icimmu_cycstb_i, icimmu_ci_i,
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ic_en, icqmem_cycstb_i, icqmem_ci_i,
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tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
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tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
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icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
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icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
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burst, tag_we
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burst, tag_we
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);
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);
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// I/O
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// I/O
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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input ic_en;
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input ic_en;
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input icimmu_cycstb_i;
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input icqmem_cycstb_i;
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input icimmu_ci_i;
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input icqmem_ci_i;
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input tagcomp_miss;
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input tagcomp_miss;
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input biudata_valid;
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input biudata_valid;
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input biudata_error;
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input biudata_error;
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input [31:0] start_addr;
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input [31:0] start_addr;
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output [31:0] saved_addr;
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output [31:0] saved_addr;
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//
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//
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// Assert for cache hit first word ready
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// Assert for cache hit first word ready
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded with an error
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// Assert for cache miss first word stored/loaded with an error
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//
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//
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assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icimmu_ci_i;
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assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icqmem_ci_i;
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assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
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assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
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assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
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assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
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//
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//
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// Assert burst when doing reload of complete cache line
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// Assert burst when doing reload of complete cache line
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Line 190... |
cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else
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else
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case (state) // synopsys parallel_case
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case (state) // synopsys parallel_case
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`OR1200_ICFSM_IDLE :
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`OR1200_ICFSM_IDLE :
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if (ic_en & icimmu_cycstb_i) begin // fetch
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if (ic_en & icqmem_cycstb_i) begin // fetch
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state <= #1 `OR1200_ICFSM_CFETCH;
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state <= #1 `OR1200_ICFSM_CFETCH;
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saved_addr_r <= #1 start_addr;
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saved_addr_r <= #1 start_addr;
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hitmiss_eval <= #1 1'b1;
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hitmiss_eval <= #1 1'b1;
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load <= #1 1'b1;
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load <= #1 1'b1;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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`OR1200_ICFSM_CFETCH: begin // fetch
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`OR1200_ICFSM_CFETCH: begin // fetch
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if (icimmu_cycstb_i & icimmu_ci_i)
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if (icqmem_cycstb_i & icqmem_ci_i)
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cache_inhibit <= #1 1'b1;
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cache_inhibit <= #1 1'b1;
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if (hitmiss_eval)
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if (hitmiss_eval)
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saved_addr_r[31:13] <= #1 start_addr[31:13];
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saved_addr_r[31:13] <= #1 start_addr[31:13];
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if ((!ic_en) ||
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if ((!ic_en) ||
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(hitmiss_eval & !icimmu_cycstb_i) || // fetch aborted (usually caused by IMMU)
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(hitmiss_eval & !icqmem_cycstb_i) || // fetch aborted (usually caused by IMMU)
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(biudata_error) || // fetch terminated with an error
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(biudata_error) || // fetch terminated with an error
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(cache_inhibit & biudata_valid)) begin // fetch from cache-inhibited page
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(cache_inhibit & biudata_valid)) begin // fetch from cache-inhibited page
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill
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else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill
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state <= #1 `OR1200_ICFSM_LREFILL3;
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state <= #1 `OR1200_ICFSM_LREFILL3;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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cnt <= #1 `OR1200_ICLS-2;
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cnt <= #1 `OR1200_ICLS-2;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else if (!tagcomp_miss & !icimmu_ci_i) begin // fetch hit, finish immediately
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else if (!tagcomp_miss & !icqmem_ci_i) begin // fetch hit, finish immediately
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saved_addr_r <= #1 start_addr;
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saved_addr_r <= #1 start_addr;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else if (!icimmu_cycstb_i) begin // fetch aborted (usually caused by exception)
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else if (!icqmem_cycstb_i) begin // fetch aborted (usually caused by exception)
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else // fetch in-progress
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else // fetch in-progress
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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end
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end
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`OR1200_ICFSM_LREFILL3 : begin
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`OR1200_ICFSM_LREFILL3 : begin
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if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
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if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
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cnt <= #1 cnt - 'd1;
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cnt <= #1 cnt - 1'd1;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
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end
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end
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else if (biudata_valid) begin // last fetch of line refill
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else if (biudata_valid) begin // last fetch of line refill
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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saved_addr_r <= #1 start_addr;
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saved_addr_r <= #1 start_addr;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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