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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Diff between revs 589 and 596

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Rev 589 Rev 596
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.2  2002/01/18 07:56:00  lampret
 
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
 
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
//
// Revision 1.12  2001/11/23 21:42:31  simons
// Revision 1.12  2001/11/23 21:42:31  simons
// Program counter divided to PPC and NPC.
// Program counter divided to PPC and NPC.
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//
//
// Supervision register
// Supervision register
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                sr <= #1 `OR1200_SR_WIDTH'b011;
                sr <= #1 `OR1200_SR_WIDTH'b001;
        else if (except_started) begin
        else if (except_started) begin
                sr[`OR1200_SR_SM] <= #1 1'b1;
                sr[`OR1200_SR_SM] <= #1 1'b1;
                sr[`OR1200_SR_TEE] <= #1 1'b0;
                sr[`OR1200_SR_TEE] <= #1 1'b0;
                sr[`OR1200_SR_IEE] <= #1 1'b0;
                sr[`OR1200_SR_IEE] <= #1 1'b0;
                sr[`OR1200_SR_DME] <= #1 1'b0;
                sr[`OR1200_SR_DME] <= #1 1'b0;

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