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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/09/03 22:28:21 lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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//
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// Revision 1.6 2002/03/29 16:40:10 lampret
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// Revision 1.6 2002/03/29 16:40:10 lampret
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// Added a directive to ignore signed division variables that are only used in simulation.
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// Added a directive to ignore signed division variables that are only used in simulation.
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//
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//
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// Revision 1.5 2002/03/29 16:33:59 lampret
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// Revision 1.5 2002/03/29 16:33:59 lampret
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// Added again just recently removed full_case directive
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// Added again just recently removed full_case directive
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_alu(
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module or1200_alu(
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a, b, mult_mac_result, macrc_op,
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a, b, mult_mac_result, macrc_op,
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alu_op, shrot_op, comp_op,
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alu_op, shrot_op, comp_op,
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result, flagforw, flag_we
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result, flagforw, flag_we,
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cyforw, cy_we, carry
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);
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);
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parameter width = `OR1200_OPERAND_WIDTH;
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parameter width = `OR1200_OPERAND_WIDTH;
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//
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//
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input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
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input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
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output [width-1:0] result;
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output [width-1:0] result;
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output flagforw;
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output flagforw;
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output flag_we;
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output flag_we;
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output cyforw;
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output cy_we;
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input carry;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [width-1:0] result;
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reg [width-1:0] result;
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reg [width-1:0] shifted_rotated;
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reg [width-1:0] shifted_rotated;
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reg flagforw;
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reg flagforw;
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reg flagcomp;
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reg flagcomp;
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reg flag_we;
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reg flag_we;
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reg cy_we;
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// synopsys translate_off
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// synopsys translate_off
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`ifdef OR1200_SIM_ALU_DIV
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`ifdef OR1200_SIM_ALU_DIV
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integer d1;
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integer d1;
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integer d2;
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integer d2;
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`endif
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`endif
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
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wire a_eq_b;
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wire a_eq_b;
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wire a_lt_b;
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wire a_lt_b;
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`endif
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`endif
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wire [width-1:0] result_sum;
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wire [width-1:0] result_sum;
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`ifdef OR1200_IMPL_ADDC
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wire [width-1:0] result_csum;
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`endif
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wire [width-1:0] result_and;
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wire [width-1:0] result_and;
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wire cyforw;
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//
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//
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// Combinatorial logic
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// Combinatorial logic
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//
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//
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
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assign a_eq_b = (comp_a == comp_b);
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assign a_eq_b = (comp_a == comp_b);
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assign a_lt_b = (comp_a < comp_b);
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assign a_lt_b = (comp_a < comp_b);
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`endif
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`endif
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assign result_sum = a + b;
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assign {cyforw, result_sum} = a + b;
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`ifdef OR1200_IMPL_ADDC
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assign {cyforw, result_csum} = a + b + carry;
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`endif
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assign result_and = a & b;
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assign result_and = a & b;
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//
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//
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// Simulation check for bad ALU behavior
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// Simulation check for bad ALU behavior
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//
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//
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result = shifted_rotated;
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result = shifted_rotated;
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end
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end
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`OR1200_ALUOP_ADD : begin
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`OR1200_ALUOP_ADD : begin
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result = result_sum;
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result = result_sum;
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end
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end
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADDC : begin
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result = result_csum;
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end
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`endif
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`OR1200_ALUOP_SUB : begin
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`OR1200_ALUOP_SUB : begin
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result = a - b;
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result = a - b;
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end
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end
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`OR1200_ALUOP_XOR : begin
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`OR1200_ALUOP_XOR : begin
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result = a ^ b;
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result = a ^ b;
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//
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//
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// Generate flag and flag write enable
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// Generate flag and flag write enable
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//
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//
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always @(alu_op or result_sum or result_and or flagcomp) begin
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always @(alu_op or result_sum or result_and or flagcomp) begin
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casex (alu_op) // synopsys parallel_case
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casex (alu_op) // synopsys parallel_case
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`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
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`OR1200_ALUOP_ADD : begin
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`OR1200_ALUOP_ADD : begin
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flagforw = (result_sum == 32'h0000_0000);
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flagforw = (result_sum == 32'h0000_0000);
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flag_we = 1'b0;
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flag_we = 1'b1;
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end
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADDC : begin
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flagforw = (result_csum == 32'h0000_0000);
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flag_we = 1'b1;
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end
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end
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`endif
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`OR1200_ALUOP_AND: begin
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`OR1200_ALUOP_AND: begin
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flagforw = (result_and == 32'h0000_0000);
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flagforw = (result_and == 32'h0000_0000);
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flag_we = 1'b0;
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flag_we = 1'b1;
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end
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end
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`endif
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`OR1200_ALUOP_COMP: begin
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`OR1200_ALUOP_COMP: begin
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flagforw = flagcomp;
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flagforw = flagcomp;
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flag_we = 1'b1;
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flag_we = 1'b1;
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end
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end
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default: begin
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default: begin
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Line 284... |
end
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end
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endcase
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endcase
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end
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end
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//
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//
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// Generate SR[CY] write enable
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//
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always @(alu_op) begin
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casex (alu_op) // synopsys parallel_case
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADDC : begin
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cy_we = 1'b1;
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end
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`endif
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default: begin
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cy_we = 1'b0;
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end
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endcase
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end
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//
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// Shifts and rotation
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// Shifts and rotation
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//
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//
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always @(shrot_op or a or b) begin
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always @(shrot_op or a or b) begin
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case (shrot_op) // synopsys parallel_case
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case (shrot_op) // synopsys parallel_case
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`OR1200_SHROTOP_SLL :
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`OR1200_SHROTOP_SLL :
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