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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/01/28 01:15:59 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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Line 109... |
reg [width-1:0] result;
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reg [width-1:0] result;
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reg [width-1:0] shifted_rotated;
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reg [width-1:0] shifted_rotated;
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reg flagforw;
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reg flagforw;
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reg flagcomp;
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reg flagcomp;
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reg flag_we;
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reg flag_we;
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`ifdef OR1200_SIM_ALU_DIV
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integer d1;
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integer d1;
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integer d2;
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integer d2;
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`endif
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_b;
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wire [width-1:0] comp_b;
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
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wire a_eq_b;
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wire a_eq_b;
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wire a_lt_b;
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wire a_lt_b;
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| Line 145... |
Line 150... |
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//
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//
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// Central part of the ALU
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// Central part of the ALU
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//
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//
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always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
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always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
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casex (alu_op) // synopsys parallel_case full_case
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casex (alu_op) // synopsys parallel_case
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`OR1200_ALUOP_SHROT : begin
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`OR1200_ALUOP_SHROT : begin
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result = shifted_rotated;
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result = shifted_rotated;
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end
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end
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`OR1200_ALUOP_ADD : begin
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`OR1200_ALUOP_ADD : begin
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result = result_sum;
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result = result_sum;
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| Line 211... |
Line 216... |
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//
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//
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// Generate flag and flag write enable
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// Generate flag and flag write enable
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//
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//
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always @(alu_op or result_sum or result_and or flagcomp) begin
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always @(alu_op or result_sum or result_and or flagcomp) begin
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casex (alu_op) // synopsys parallel_case full_case
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casex (alu_op) // synopsys parallel_case
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`OR1200_ALUOP_ADD : begin
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`OR1200_ALUOP_ADD : begin
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flagforw = (result_sum == 32'h0000_0000);
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flagforw = (result_sum == 32'h0000_0000);
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flag_we = 1'b0;
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flag_we = 1'b0;
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end
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end
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`OR1200_ALUOP_AND: begin
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`OR1200_ALUOP_AND: begin
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Line 260... |
//
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//
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// First type of compare implementation
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// First type of compare implementation
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//
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//
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
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always @(comp_op or a_eq_b or a_lt_b) begin
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always @(comp_op or a_eq_b or a_lt_b) begin
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case(comp_op[2:0]) // synopsys parallel_case full_case
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case(comp_op[2:0]) // synopsys parallel_case
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`OR1200_COP_SFEQ:
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`OR1200_COP_SFEQ:
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flagcomp = a_eq_b;
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flagcomp = a_eq_b;
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`OR1200_COP_SFNE:
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`OR1200_COP_SFNE:
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flagcomp = ~a_eq_b;
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flagcomp = ~a_eq_b;
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`OR1200_COP_SFGT:
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`OR1200_COP_SFGT:
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Line 284... |
//
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//
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// Second type of compare implementation
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// Second type of compare implementation
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//
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//
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`ifdef OR1200_IMPL_ALU_COMP2
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`ifdef OR1200_IMPL_ALU_COMP2
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always @(comp_op or comp_a or comp_b) begin
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always @(comp_op or comp_a or comp_b) begin
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case(comp_op[2:0]) // synopsys parallel_case full_case
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case(comp_op[2:0]) // synopsys parallel_case
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`OR1200_COP_SFEQ:
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`OR1200_COP_SFEQ:
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flagcomp = (comp_a == comp_b);
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flagcomp = (comp_a == comp_b);
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`OR1200_COP_SFNE:
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`OR1200_COP_SFNE:
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flagcomp = (comp_a != comp_b);
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flagcomp = (comp_a != comp_b);
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`OR1200_COP_SFGT:
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`OR1200_COP_SFGT:
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