| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.19 2001/11/30 18:59:47 simons
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// Revision 1.19 2001/11/30 18:59:47 simons
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// *** empty log message ***
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// *** empty log message ***
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| Line 121... |
Line 124... |
dc_en,
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dc_en,
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dcpu_adr_o, dcpu_cyc_o, dcpu_stb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_adr_o, dcpu_cyc_o, dcpu_stb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
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dmmu_en,
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dmmu_en,
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|
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// Interrupt exceptions
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// Interrupt & tick exceptions
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int_high, int_low,
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sig_int, sig_tick,
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|
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// SPR interface
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// SPR interface
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supv, spr_addr, spr_dataout, spr_dat_pic, spr_dat_tt, spr_dat_pm,
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supv, spr_addr, spr_dataout, spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we
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spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we
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);
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);
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| Line 218... |
Line 221... |
output spr_we;
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output spr_we;
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|
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//
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//
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// Interrupt exceptions
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// Interrupt exceptions
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//
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//
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input int_high;
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input sig_int;
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input int_low;
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input sig_tick;
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|
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//
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//
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// Internal wires
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// Internal wires
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//
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//
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wire [31:0] if_insn;
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wire [31:0] if_insn;
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| Line 341... |
Line 344... |
assign immu_en = sr[`OR1200_SR_IME];
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assign immu_en = sr[`OR1200_SR_IME];
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|
|
//
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//
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// SUPV bit
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// SUPV bit
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//
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//
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assign supv = sr[`OR1200_SR_SUPV];
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assign supv = sr[`OR1200_SR_SM];
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|
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//
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//
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// Instantiation of instruction fetch block
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// Instantiation of instruction fetch block
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//
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//
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or1200_genpc or1200_genpc(
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or1200_genpc or1200_genpc(
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| Line 362... |
Line 365... |
.icpu_adr_i(icpu_adr_i),
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.icpu_adr_i(icpu_adr_i),
|
|
|
.branch_op(branch_op),
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.branch_op(branch_op),
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.except_type(except_type),
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.except_type(except_type),
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.except_start(except_start),
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.except_start(except_start),
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.except_prefix(sr[`OR1200_SR_EPH]),
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.branch_addrofs(branch_addrofs),
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.branch_addrofs(branch_addrofs),
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.lr_restor(operand_b),
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.lr_restor(operand_b),
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.flag(flag),
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.flag(flag),
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.taken(branch_taken),
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.taken(branch_taken),
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.binsn_addr(lr_sav),
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.binsn_addr(lr_sav),
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| Line 451... |
Line 455... |
// Instantiation of register file
|
// Instantiation of register file
|
//
|
//
|
or1200_rf or1200_rf(
|
or1200_rf or1200_rf(
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.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.supv(sr[`OR1200_SR_SUPV]),
|
.supv(sr[`OR1200_SR_SM]),
|
.wb_freeze(wb_freeze),
|
.wb_freeze(wb_freeze),
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.addrw(rf_addrw),
|
.addrw(rf_addrw),
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.dataw(rf_dataw),
|
.dataw(rf_dataw),
|
.id_freeze(id_freeze),
|
.id_freeze(id_freeze),
|
.we(rfwb_op[0]),
|
.we(rfwb_op[0]),
|
| Line 593... |
Line 597... |
.lsu_datain(operand_b),
|
.lsu_datain(operand_b),
|
.lsu_dataout(lsu_dataout),
|
.lsu_dataout(lsu_dataout),
|
.lsu_stall(lsu_stall),
|
.lsu_stall(lsu_stall),
|
.lsu_unstall(lsu_unstall),
|
.lsu_unstall(lsu_unstall),
|
.du_stall(du_stall),
|
.du_stall(du_stall),
|
|
.flushpipe(flushpipe),
|
.except_align(except_align),
|
.except_align(except_align),
|
.except_dtlbmiss(except_dtlbmiss),
|
.except_dtlbmiss(except_dtlbmiss),
|
.except_dmmufault(except_dmmufault),
|
.except_dmmufault(except_dmmufault),
|
.except_dbuserr(except_dbuserr),
|
.except_dbuserr(except_dbuserr),
|
|
|
| Line 664... |
Line 669... |
.sig_illegal(except_illegal),
|
.sig_illegal(except_illegal),
|
.sig_align(except_align),
|
.sig_align(except_align),
|
.sig_range(1'b0),
|
.sig_range(1'b0),
|
.sig_dtlbmiss(except_dtlbmiss),
|
.sig_dtlbmiss(except_dtlbmiss),
|
.sig_dmmufault(except_dmmufault),
|
.sig_dmmufault(except_dmmufault),
|
.sig_inthigh(int_high),
|
.sig_int(sig_int),
|
.sig_syscall(sig_syscall),
|
.sig_syscall(sig_syscall),
|
.sig_trap(sig_trap),
|
.sig_trap(sig_trap),
|
.sig_itlbmiss(except_itlbmiss),
|
.sig_itlbmiss(except_itlbmiss),
|
.sig_immufault(except_immufault),
|
.sig_immufault(except_immufault),
|
.sig_intlow(int_low),
|
.sig_tick(sig_tick),
|
.branch_taken(branch_taken),
|
.branch_taken(branch_taken),
|
.id_freeze(id_freeze),
|
.id_freeze(id_freeze),
|
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.wb_freeze(wb_freeze),
|
.wb_freeze(wb_freeze),
|
.if_stall(if_stall),
|
.if_stall(if_stall),
|
| Line 683... |
Line 688... |
.extend_flush(extend_flush),
|
.extend_flush(extend_flush),
|
.except_type(except_type),
|
.except_type(except_type),
|
.except_start(except_start),
|
.except_start(except_start),
|
.except_started(except_started),
|
.except_started(except_started),
|
.except_stop(except_stop),
|
.except_stop(except_stop),
|
.wb_pc(spr_dat_ppc),
|
.has_dslot(has_dslot),
|
.ex_pc(spr_dat_npc),
|
.spr_dat_ppc(spr_dat_ppc),
|
.id_pc(),
|
.spr_dat_npc(spr_dat_npc),
|
// .wb_pc(),
|
|
// .ex_pc(spr_dat_ppc),
|
|
// .id_pc(spr_dat_npc),
|
|
|
|
.datain(operand_b),
|
.datain(operand_b),
|
.du_dsr(du_dsr),
|
.du_dsr(du_dsr),
|
.epcr_we(epcr_we),
|
.epcr_we(epcr_we),
|
.eear_we(eear_we),
|
.eear_we(eear_we),
|
