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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_ctrl.v] - Diff between revs 788 and 1032

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Rev 788	Rev 1032
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.6 2002/03/29 15:16:54 lampret`
	`// Some of the warnings fixed.`
	`//`
`// Revision 1.5 2002/02/01 19:56:54 lampret`	`// Revision 1.5 2002/02/01 19:56:54 lampret`
`// Fixed combinational loops.`	`// Fixed combinational loops.`
`//`	`//`
`// Revision 1.4 2002/01/28 01:15:59 lampret`	`// Revision 1.4 2002/01/28 01:15:59 lampret`
`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`	`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
Line 625...	Line 628...
`OR1200_OR32_ADDI:	`OR1200_OR32_ADDI:
alu_op <= #1 `OR1200_ALUOP_ADD;	alu_op <= #1 `OR1200_ALUOP_ADD;

`// l.addic`	`// l.addic`
`OR1200_OR32_ADDIC:	`OR1200_OR32_ADDIC:
alu_op <= #1 `OR1200_ALUOP_ADD;	alu_op <= #1 `OR1200_ALUOP_ADDC;

`// l.andi`	`// l.andi`
`OR1200_OR32_ANDI:	`OR1200_OR32_ANDI:
alu_op <= #1 `OR1200_ALUOP_AND;	alu_op <= #1 `OR1200_ALUOP_AND;

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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_ctrl.v] - Diff between revs 788 and 1032