| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.3 2002/01/18 14:21:43 lampret
|
|
// Fixed 'the NPC single-step fix'.
|
|
//
|
// Revision 1.2 2002/01/14 06:18:22 lampret
|
// Revision 1.2 2002/01/14 06:18:22 lampret
|
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
|
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
|
//
|
//
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
| Line 93... |
Line 96... |
module or1200_ctrl(
|
module or1200_ctrl(
|
// Clock and reset
|
// Clock and reset
|
clk, rst,
|
clk, rst,
|
|
|
// Internal i/f
|
// Internal i/f
|
id_freeze, ex_freeze, wb_freeze, flushpipe, if_insn, ex_insn, branch_op,
|
id_freeze, ex_freeze, wb_freeze, flushpipe, if_insn, ex_insn, branch_op, branch_taken,
|
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op,
|
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op,
|
wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
|
wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
|
multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap,
|
multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap,
|
force_dslot_fetch, has_dslot, ex_void, id_macrc_op, ex_macrc_op, rfe, except_illegal
|
force_dslot_fetch, no_more_dslot, ex_void, id_macrc_op, ex_macrc_op, rfe, except_illegal
|
);
|
);
|
|
|
//
|
//
|
// I/O
|
// I/O
|
//
|
//
|
| Line 112... |
Line 115... |
input wb_freeze;
|
input wb_freeze;
|
input flushpipe;
|
input flushpipe;
|
input [31:0] if_insn;
|
input [31:0] if_insn;
|
output [31:0] ex_insn;
|
output [31:0] ex_insn;
|
output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
|
output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
|
|
input branch_taken;
|
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
|
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
|
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
|
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
|
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
|
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
|
output rf_rda;
|
output rf_rda;
|
output rf_rdb;
|
output rf_rdb;
|
| Line 135... |
Line 139... |
output [15:0] spr_addrimm;
|
output [15:0] spr_addrimm;
|
input wbforw_valid;
|
input wbforw_valid;
|
output sig_syscall;
|
output sig_syscall;
|
output sig_trap;
|
output sig_trap;
|
output force_dslot_fetch;
|
output force_dslot_fetch;
|
output has_dslot;
|
output no_more_dslot;
|
output ex_void;
|
output ex_void;
|
output id_macrc_op;
|
output id_macrc_op;
|
output ex_macrc_op;
|
output ex_macrc_op;
|
output rfe;
|
output rfe;
|
output except_illegal;
|
output except_illegal;
|
| Line 186... |
Line 190... |
// instructions
|
// instructions
|
//
|
//
|
// SIMON
|
// SIMON
|
// assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op));
|
// assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op));
|
assign force_dslot_fetch = 1'b0;
|
assign force_dslot_fetch = 1'b0;
|
assign has_dslot = |branch_op & !id_void;
|
assign no_more_dslot = |branch_op & !id_void & branch_taken | (branch_op == `OR1200_BRANCHOP_RFE);
|
assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[0];
|
assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
|
assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0];
|
assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
|
|
|
//
|
//
|
// Sign/Zero extension of immediates
|
// Sign/Zero extension of immediates
|
//
|
//
|
assign simm = (imm_signextend == 1'b1) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
|
assign simm = (imm_signextend == 1'b1) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
|
| Line 401... |
Line 405... |
//
|
//
|
// Instruction latch in id_insn
|
// Instruction latch in id_insn
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
id_insn <= #1 {`OR1200_OR32_NOP, 26'h000_444F};
|
id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
|
else if (flushpipe)
|
else if (flushpipe)
|
id_insn <= #1 {`OR1200_OR32_NOP, 26'h000_444F}; // id_insn[0] must be 1
|
id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // id_insn[16] must be 1
|
else if (!id_freeze) begin
|
else if (!id_freeze) begin
|
id_insn <= #1 if_insn;
|
id_insn <= #1 if_insn;
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("%t: id_insn <= %h", $time, if_insn);
|
$display("%t: id_insn <= %h", $time, if_insn);
|
| Line 419... |
Line 423... |
//
|
//
|
// Instruction latch in ex_insn
|
// Instruction latch in ex_insn
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
ex_insn <= #1 {`OR1200_OR32_NOP, 26'h000_444F};
|
ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
|
else if (!ex_freeze & id_freeze | flushpipe)
|
else if (!ex_freeze & id_freeze | flushpipe)
|
ex_insn <= #1 {`OR1200_OR32_NOP, 26'h000_444F}; // ex_insn[0] must be 1
|
ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // ex_insn[16] must be 1
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
ex_insn <= #1 id_insn;
|
ex_insn <= #1 id_insn;
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("%t: ex_insn <= %h", $time, id_insn);
|
$display("%t: ex_insn <= %h", $time, id_insn);
|
| Line 437... |
Line 441... |
//
|
//
|
// Instruction latch in wb_insn
|
// Instruction latch in wb_insn
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h000_444F};
|
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
|
else if (flushpipe)
|
else if (flushpipe)
|
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h000_444F}; // wb_insn[0] must be 1
|
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // wb_insn[16] must be 1
|
else if (!wb_freeze) begin
|
else if (!wb_freeze) begin
|
wb_insn <= #1 ex_insn;
|
wb_insn <= #1 ex_insn;
|
end
|
end
|
end
|
end
|
|
|
