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// Revision 1.22  2002/09/03 22:28:21  lampret

// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.

//

/////////////////////////////////////////////////////

//

// VR, UPR and Configuration Registers

//

//

// VR, UPR and configuration registers are optional. If 

// implemented, operating system can automatically figure

// out how to use the processor because it knows 

// what units are available in the processor and how they

// are configured.

//

// This section must be last in or1200_defines.v file so

// that all units are already configured and thus

// configuration registers are properly set.

// 

// Define if you want configuration registers implemented

`define OR1200_CFGR_IMPLEMENTED

// Define if you want full address decode inside SYS group

`define OR1200_SYS_FULL_DECODE

// Offsets of VR, UPR and CFGR registers

`define OR1200_SPRGRP_SYS_VR            4'h0

`define OR1200_SPRGRP_SYS_UPR           4'h1

`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2

`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3

`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4

`define OR1200_SPRGRP_SYS_DCCFGR        4'h5

`define OR1200_SPRGRP_SYS_ICCFGR        4'h6

`define OR1200_SPRGRP_SYS_DCFGR 4'h7

// VR fields

`define OR1200_VR_REV_BITS              5:0

`define OR1200_VR_RES1_BITS             15:6

`define OR1200_VR_CFG_BITS              23:16

`define OR1200_VR_VER_BITS              31:24

// VR values

`define OR1200_VR_REV                   6'h00

`define OR1200_VR_RES1                  10'h000

`define OR1200_VR_CFG                   8'h00

`define OR1200_VR_VER                   8'h12

// UPR fields

`define OR1200_UPR_UP_BITS              0

`define OR1200_UPR_DCP_BITS             1

`define OR1200_UPR_ICP_BITS             2

`define OR1200_UPR_DMP_BITS             3

`define OR1200_UPR_IMP_BITS             4

`define OR1200_UPR_MP_BITS              5

`define OR1200_UPR_DUP_BITS             6

`define OR1200_UPR_PCUP_BITS            7

`define OR1200_UPR_PMP_BITS             8

`define OR1200_UPR_PICP_BITS            9

`define OR1200_UPR_TTP_BITS             10

`define OR1200_UPR_RES1_BITS            23:11

`define OR1200_UPR_CUP_BITS             31:24

// UPR values

`define OR1200_UPR_UP                   1'b1

`ifdef OR1200_NO_DC

`define OR1200_UPR_DCP                  1'b0

`else

`define OR1200_UPR_DCP                  1'b1

`endif

`ifdef OR1200_NO_IC

`define OR1200_UPR_ICP                  1'b0

`else

`define OR1200_UPR_ICP                  1'b1

`endif

`ifdef OR1200_NO_DMMU

`define OR1200_UPR_DMP                  1'b0

`else

`define OR1200_UPR_DMP                  1'b1

`endif

`ifdef OR1200_NO_IMMU

`define OR1200_UPR_IMP                  1'b0

`else

`define OR1200_UPR_IMP                  1'b1

`endif

`define OR1200_UPR_MP                   1'b1    // MAC always present

`ifdef OR1200_DU_IMPLEMENTED

`define OR1200_UPR_DUP                  1'b1

`else

`define OR1200_UPR_DUP                  1'b0

`endif

`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present

`ifdef OR1200_DU_IMPLEMENTED

`define OR1200_UPR_PMP                  1'b1

`else

`define OR1200_UPR_PMP                  1'b0

`endif

`ifdef OR1200_DU_IMPLEMENTED

`define OR1200_UPR_PICP                 1'b1

`else

`define OR1200_UPR_PICP                 1'b0

`endif

`ifdef OR1200_DU_IMPLEMENTED

`define OR1200_UPR_TTP                  1'b1

`else

`define OR1200_UPR_TTP                  1'b0

`endif

`define OR1200_UPR_RES1                 13'h0000

`define OR1200_UPR_CUP                  8'h00

// CPUCFGR fields

`define OR1200_CPUCFGR_NSGF_BITS        3:0

`define OR1200_CPUCFGR_HGF_BITS 4

`define OR1200_CPUCFGR_OB32S_BITS       5

`define OR1200_CPUCFGR_OB64S_BITS       6

`define OR1200_CPUCFGR_OF32S_BITS       7

`define OR1200_CPUCFGR_OF64S_BITS       8

`define OR1200_CPUCFGR_OV64S_BITS       9

`define OR1200_CPUCFGR_RES1_BITS        31:10

// CPUCFGR values

`define OR1200_CPUCFGR_NSGF             4'h0

`define OR1200_CPUCFGR_HGF              1'b0

`define OR1200_CPUCFGR_OB32S            1'b1

`define OR1200_CPUCFGR_OB64S            1'b0

`define OR1200_CPUCFGR_OF32S            1'b0

`define OR1200_CPUCFGR_OF64S            1'b0

`define OR1200_CPUCFGR_OV64S            1'b0

`define OR1200_CPUCFGR_RES1             22'h000000

// DMMUCFGR fields

`define OR1200_DMMUCFGR_NTW_BITS        1:0

`define OR1200_DMMUCFGR_NTS_BITS        4:2

`define OR1200_DMMUCFGR_NAE_BITS        7:5

`define OR1200_DMMUCFGR_CRI_BITS        8

`define OR1200_DMMUCFGR_PRI_BITS        9

`define OR1200_DMMUCFGR_TEIRI_BITS      10

`define OR1200_DMMUCFGR_HTR_BITS        11

`define OR1200_DMMUCFGR_RES1_BITS       31:12

// DMMUCFGR values

`ifdef OR1200_NO_DMMU

`define OR1200_DMMUCFGR_NTW             2'h0    // Irrelevant

`define OR1200_DMMUCFGR_NTS             3'h0    // Irrelevant

`define OR1200_DMMUCFGR_NAE             3'h0    // Irrelevant

`define OR1200_DMMUCFGR_CRI             1'b0    // Irrelevant

`define OR1200_DMMUCFGR_PRI             1'b0    // Irrelevant

`define OR1200_DMMUCFGR_TEIRI           1'b0    // Irrelevant

`define OR1200_DMMUCFGR_HTR             1'b0    // Irrelevant

`define OR1200_DMMUCFGR_RES1            20'h00000

`else

`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way

`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets

`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries

`define OR1200_DMMUCFGR_CRI             1'b0    // No control register

`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg

`define OR1200_DMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl.

`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload

`define OR1200_DMMUCFGR_RES1            20'h00000

`endif

// IMMUCFGR fields

`define OR1200_IMMUCFGR_NTW_BITS        1:0

`define OR1200_IMMUCFGR_NTS_BITS        4:2

`define OR1200_IMMUCFGR_NAE_BITS        7:5

`define OR1200_IMMUCFGR_CRI_BITS        8

`define OR1200_IMMUCFGR_PRI_BITS        9

`define OR1200_IMMUCFGR_TEIRI_BITS      10

`define OR1200_IMMUCFGR_HTR_BITS        11

`define OR1200_IMMUCFGR_RES1_BITS       31:12

// IMMUCFGR values

`ifdef OR1200_NO_IMMU

`define OR1200_IMMUCFGR_NTW             2'h0    // Irrelevant

`define OR1200_IMMUCFGR_NTS             3'h0    // Irrelevant

`define OR1200_IMMUCFGR_NAE             3'h0    // Irrelevant

`define OR1200_IMMUCFGR_CRI             1'b0    // Irrelevant

`define OR1200_IMMUCFGR_PRI             1'b0    // Irrelevant

`define OR1200_IMMUCFGR_TEIRI           1'b0    // Irrelevant

`define OR1200_IMMUCFGR_HTR             1'b0    // Irrelevant

`define OR1200_IMMUCFGR_RES1            20'h00000

`else

`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way

`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets

`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry

`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg

`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg

`define OR1200_IMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl

`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload

`define OR1200_IMMUCFGR_RES1            20'h00000

`endif

// DCCFGR fields

`define OR1200_DCCFGR_NCW_BITS          2:0

`define OR1200_DCCFGR_NCS_BITS          6:3

`define OR1200_DCCFGR_CBS_BITS          7

`define OR1200_DCCFGR_CWS_BITS          8

`define OR1200_DCCFGR_CCRI_BITS         9

`define OR1200_DCCFGR_CBIRI_BITS        10

`define OR1200_DCCFGR_CBPRI_BITS        11

`define OR1200_DCCFGR_CBLRI_BITS        12

`define OR1200_DCCFGR_CBFRI_BITS        13

`define OR1200_DCCFGR_CBWBRI_BITS       14

`define OR1200_DCCFGR_RES1_BITS 31:15

// DCCFGR values

`ifdef OR1200_NO_DC

`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant

`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant

`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant

`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant

`define OR1200_DCCFGR_CCRI              1'b1    // Irrelevant

`define OR1200_DCCFGR_CBIRI             1'b1    // Irrelevant

`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant

`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant

`define OR1200_DCCFGR_CBFRI             1'b1    // Irrelevant

`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant

`define OR1200_DCCFGR_RES1              17'h00000

`else

`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way

`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets

`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4)      // 16 byte cache block

`define OR1200_DCCFGR_CWS               1'b0    // Write-through strategy

`define OR1200_DCCFGR_CCRI              1'b1    // Cache control reg impl.

`define OR1200_DCCFGR_CBIRI             1'b1    // Cache block inv reg impl.

`define OR1200_DCCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.

`define OR1200_DCCFGR_CBLRI             1'b0    // Cache block lock reg not impl.

`define OR1200_DCCFGR_CBFRI             1'b1    // Cache block flush reg impl.

`define OR1200_DCCFGR_CBWBRI            1'b0    // Cache block WB reg not impl.

`define OR1200_DCCFGR_RES1              17'h00000

`endif

// ICCFGR fields

`define OR1200_ICCFGR_NCW_BITS          2:0

`define OR1200_ICCFGR_NCS_BITS          6:3

`define OR1200_ICCFGR_CBS_BITS          7

`define OR1200_ICCFGR_CWS_BITS          8

`define OR1200_ICCFGR_CCRI_BITS         9

`define OR1200_ICCFGR_CBIRI_BITS        10

`define OR1200_ICCFGR_CBPRI_BITS        11

`define OR1200_ICCFGR_CBLRI_BITS        12

`define OR1200_ICCFGR_CBFRI_BITS        13

`define OR1200_ICCFGR_CBWBRI_BITS       14

`define OR1200_ICCFGR_RES1_BITS 31:15

// ICCFGR values

`ifdef OR1200_NO_IC

`define OR1200_ICCFGR_NCW               3'h0    // Irrelevant

`define OR1200_ICCFGR_NCS               4'h0    // Irrelevant

`define OR1200_ICCFGR_CBS               1'b0    // Irrelevant

`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant

`define OR1200_ICCFGR_CCRI              1'b0    // Irrelevant

`define OR1200_ICCFGR_CBIRI             1'b0    // Irrelevant

`define OR1200_ICCFGR_CBPRI             1'b0    // Irrelevant

`define OR1200_ICCFGR_CBLRI             1'b0    // Irrelevant

`define OR1200_ICCFGR_CBFRI             1'b0    // Irrelevant

`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant

`define OR1200_ICCFGR_RES1              17'h00000

`else

`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way

`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets

`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4)      // 16 byte cache block

`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant

`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.

`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.

`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.

`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.

`define OR1200_ICCFGR_CBFRI             1'b1    // Cache block flush reg impl.

`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant

`define OR1200_ICCFGR_RES1              17'h00000

`endif

// DCFGR fields

`define OR1200_DCFGR_NDP_BITS           2:0

`define OR1200_DCFGR_WPCI_BITS          3

`define OR1200_DCFGR_RES1_BITS          31:4

// DCFGR values

`define OR1200_DCFGR_NDP                3'h0    // Zero DVR/DCR pairs

`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.

`define OR1200_DCFGR_RES1               28'h0000000