URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 1055 and 1063

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 1055	Rev 1063
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.27 2002/09/16 03:13:23 lampret`
	`// Removed obsolete comment.`
	`//`
`// Revision 1.26 2002/09/08 05:52:16 lampret`	`// Revision 1.26 2002/09/08 05:52:16 lampret`
`// Added optional l.div/l.divu insns. By default they are disabled.`	`// Added optional l.div/l.divu insns. By default they are disabled.`
`//`	`//`
`// Revision 1.25 2002/09/07 19:16:10 lampret`	`// Revision 1.25 2002/09/07 19:16:10 lampret`
`// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].`	`// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].`
Line 301...	Line 304...
`//`	`//`
`// Do not change below unless you know what you are doing`	`// Do not change below unless you know what you are doing`
`//`	`//`

`//`	`//`
	`// Enable RAM BIST`
	`//`
	`// At the moment this only works for Virtual Silicon`
	`// single port RAMs. For other RAMs it has not effect.`
	`// Special wrapper for VS RAMs needs to be provided`
	`// with scan flops to facilitate bist scan.`
	`//`
	//`define OR1200_BIST

	`//`
`// Register OR1200 WISHBONE outputs`	`// Register OR1200 WISHBONE outputs`
`// (must be defined/enabled)`	`// (must be defined/enabled)`
`//`	`//`
`define OR1200_REGISTERED_OUTPUTS	`define OR1200_REGISTERED_OUTPUTS

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 1055 and 1063